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Sun, 04 Oct 2026 09:31:27 -0700 (PDT) Received: from xeon ([188.163.112.76]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a0316b2524sm315365035e9.1.2026.10.04.09.31.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Oct 2026 09:31:27 -0700 (PDT) From: Svyatoslav Ryhel To: Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Mikko Perttunen , Svyatoslav Ryhel Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 0/7] drm/tegra: Add support for Tegra20/Tegra30 8-bit CPU interface Date: Sun, 4 Oct 2026 19:31:07 +0300 Message-ID: <20261004163114.181800-1-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The display controller in Tegra20/30 SoCs features an 8-bit SPI interface that closely resembles the MIPI DBI Type B protocol and is referred to as '8-bit CPU'. Add DC parametrization options needed for fine tuning by bridges. Add 8-bit CPU interface in form of a bridge linking to RGB port. Add 2 DBI Type B panels used in LG Optimus 2X which work with the 8-bit CPU interface. --- Changes in v2: - convert enums in the dc header into definitions list - add check in RGB if bridge_state is not NULL, if yes, use default flags - inverted FLAG_PIXDATA_SAMPLE flag setup logic since default value is set to be on NEGEDGE while v1 set default to be on POSEDGE - 8bit-cpu schema renamed to dbi, removed compaible and set as DC child - expanded list of required properties - 8bit-cpu bridge remodelled into dbi interface as DC child - improve gpio handling - rework attach to get drvdata from parent - add panel supplies description - split panel driver into per-panel drivers - get DBI interface from the patent directly I have deliberately left GPIO parsing from device tree since it seems to be the most convenient and mainstream method of working with GPIOs. --- Svyatoslav Ryhel (7): drm/tegra: dc: Expand available registers layouts drm/tegra: rgb: Parameterize configuration based on bus flags dt-bindings: display: tegra: Document 8-bit CPU parallel interface drm/tegra: Add support for 8-bit CPU interface dt-bindings: display: panel: Document Hitachi TX10D07VM0BAA and LG LH400WV3 panels drm/panel: Add Hitachi TX10D07VM0BAA MIPI DBI Type B panel driver drm/panel: Add LG LH400WV3-SD04 MIPI DBI Type B panel driver .../display/panel/hit,tx10d07vm0baa.yaml | 58 +++ .../display/tegra/nvidia,tegra-dbi.yaml | 143 ++++++ .../display/tegra/nvidia,tegra20-dc.yaml | 3 + drivers/gpu/drm/panel/Kconfig | 27 ++ drivers/gpu/drm/panel/Makefile | 2 + .../drm/panel/panel-hitachi-tx10d07vm0baa.c | 297 +++++++++++++ drivers/gpu/drm/panel/panel-lg-lh400wv3.c | 236 ++++++++++ drivers/gpu/drm/tegra/Kconfig | 7 + drivers/gpu/drm/tegra/Makefile | 1 + drivers/gpu/drm/tegra/dbi.c | 416 ++++++++++++++++++ drivers/gpu/drm/tegra/dc.c | 24 +- drivers/gpu/drm/tegra/dc.h | 50 ++- drivers/gpu/drm/tegra/rgb.c | 41 +- 13 files changed, 1293 insertions(+), 12 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/panel/hit,tx10d07vm0baa.yaml create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra-dbi.yaml create mode 100644 drivers/gpu/drm/panel/panel-hitachi-tx10d07vm0baa.c create mode 100644 drivers/gpu/drm/panel/panel-lg-lh400wv3.c create mode 100644 drivers/gpu/drm/tegra/dbi.c -- 2.53.0