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Sun, 04 Oct 2026 09:31:32 -0700 (PDT) From: Svyatoslav Ryhel To: Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Mikko Perttunen , Svyatoslav Ryhel Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 3/7] dt-bindings: display: tegra: Document 8-bit CPU parallel interface Date: Sun, 4 Oct 2026 19:31:10 +0300 Message-ID: <20261004163114.181800-4-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261004163114.181800-1-clamor95@gmail.com> References: <20261004163114.181800-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Document 8-bit CPU parallel MIPI DBI Type B interface provided by Tegra20/30 SoCs display controller. Signed-off-by: Svyatoslav Ryhel --- .../display/tegra/nvidia,tegra-dbi.yaml | 143 ++++++++++++++++++ .../display/tegra/nvidia,tegra20-dc.yaml | 3 + 2 files changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra-dbi.yaml diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra-dbi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra-dbi.yaml new file mode 100644 index 0000000000000..184c33d436308 --- /dev/null +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra-dbi.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra-dbi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nvidia Tegra DC based MIPI DBI Type B interface + +maintainers: + - Svyatoslav Ryhel + +description: The display controller in Tegra20/30 SoCs features an + 8-bit SPI interface that closely resembles the MIPI DBI Type B + protocol and is referred to as '8-bit CPU'. Each display controller + provides two such interfaces, which can be used to send MIPI DCS + commands to initialize and control the panel while image data is + transmitted via 16/18/24-line RGB. + +properties: + dc-gpios: + description: Data/command selection pin. + maxItems: 1 + + rw-gpios: + description: Read/write pin. + maxItems: 1 + + cs-gpios: + description: Chip select pin. + maxItems: 1 + + data-gpios: + description: Specifies a set of 8 gpio pins used to transfer data. + minItems: 8 + maxItems: 8 + + nvidia,init-sequence: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Device specific set of values used in DC DISP_SPI_INIT_SEQ registers. + minItems: 4 + maxItems: 4 + + panel: + type: object + description: Node of supported panel driven by the bridge. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Video port for RGB input. + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + properties: + bus-width: + enum: [ 16, 18, 24 ] + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for DBI output (panel or connector). + + required: + - port@0 + - port@1 + +required: + - compatible + - dc-gpios + - rw-gpios + - cs-gpios + - data-gpios + - panel + - ports + +unevaluatedProperties: false + +examples: + - | + #include + + dc@54200000 { + reg = <0x54200000 0x00040000>; + + dbi { + dc-gpios = <&gpio 110 GPIO_ACTIVE_HIGH>; + rw-gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio 108 GPIO_ACTIVE_HIGH>; + + data-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>, <&gpio 33 GPIO_ACTIVE_HIGH>, + <&gpio 34 GPIO_ACTIVE_HIGH>, <&gpio 35 GPIO_ACTIVE_HIGH>, + <&gpio 36 GPIO_ACTIVE_HIGH>, <&gpio 37 GPIO_ACTIVE_HIGH>, + <&gpio 38 GPIO_ACTIVE_HIGH>, <&gpio 39 GPIO_ACTIVE_HIGH>; + + nvidia,init-sequence = <0x0000002c 0x0 0x0 0x00005000>; + + panel { + compatible = "hit,tx10d07vm0baa"; + + reset-gpios = <&gpio 175 GPIO_ACTIVE_LOW>; + + avci-supply = <&vcc_2v8_lcd>; + iovcc-supply = <&iovcc_1v8_lcd>; + + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + bus-width = <24>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml index 69be95afd5627..bb280f8dbfc7c 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml @@ -76,6 +76,9 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array description: A list of phandles of outputs that this display controller can drive. + dbi: + $ref: /schemas/display/tegra/nvidia,tegra-dbi.yaml# + rgb: type: object -- 2.53.0