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From: sashiko-bot@kernel.org
To: "Jisheng Zhang" <jszhang@kernel.org>
Cc: Frank.Li@kernel.org, linux-i3c@lists.infradead.org,
	conor+dt@kernel.org,
	"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
	robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 1/3] dt-bindings: i3c: dw: support up to two reset lines
Date: Mon, 05 Oct 2026 15:51:16 +0000	[thread overview]
Message-ID: <20261005155116.83BD71F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20261005152425.25319-2-jszhang@kernel.org>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] dt-bindings: i3c: dw: maxItems mismatch with commit message
- [Low] dt-bindings: i3c: dw: missing items/reset-names for multiple resets
--

commit 6da78b08867272d83c36c1c30ce43bb39d9aaf6d
Author: Jisheng Zhang <jszhang@kernel.org>

dt-bindings: i3c: dw: support up to two reset lines

This commit updates the Synopsys DesignWare I3C master controller device tree
binding to support multiple reset lines. It increases the maxItems for the
resets property to 2 and adds a conditional block to maintain the previous
limit for the Agilex 5 variant.

> The Synopsys DesignWare I3C master controller can have multiple reset
> lines, such as core reset, apb reset, and dma reset.
> 
> Update the DT binding documentation to increase maxItems for the resets
> property to 2.

[Severity: Medium]
The commit message explicitly lists three distinct reset lines (core reset,
apb reset, and dma reset). Does limiting the property to 2 directly
contradict the hardware capabilities described?

A hardware configuration wired with all three resets would fail schema
validation, and the follow-up patches in the series do not appear to fix
this mismatch.

> diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> --- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
[ ... ]
> @@ -39,7 +49,7 @@ properties:
>      maxItems: 1
>  
>    resets:
> -    maxItems: 1
> +    maxItems: 2

[Severity: Low]
When allowing multiple items in an array, does the schema need to document
the exact order (via an items list) or require reset-names?

Without a strict documented order or reset-names, the OS-independent ABI
remains ambiguous. Although a follow-up patch in this series (commit "i3c:
dw: switch to array-based exclusive reset control") updates the Linux driver
to use devm_reset_control_array_get_optional_exclusive to fetch all resets
regardless of order, the device tree binding itself remains incomplete.

Other OSes or future drivers that may need to toggle these distinct reset
lines sequentially currently have no ABI to rely on.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261005152425.25319-1-jszhang@kernel.org?part=1

  reply	other threads:[~2026-10-05 15:51 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-05 15:24 [PATCH v2 0/3] i3c: dw: Support Synaptics sl2610 i3c Jisheng Zhang
2026-10-05 15:24 ` [PATCH v2 1/3] dt-bindings: i3c: dw: support up to two reset lines Jisheng Zhang
2026-10-05 15:51   ` sashiko-bot [this message]
2026-10-07 10:37   ` Conor Dooley
2026-10-05 15:24 ` [PATCH v2 2/3] i3c: dw: switch to array-based exclusive reset control Jisheng Zhang
2026-10-05 15:24 ` [PATCH v2 3/3] dt-bindings: i3c: Add Synaptics sl2610 i3c Jisheng Zhang
2026-10-07 10:37   ` Conor Dooley
2026-10-08 12:22 ` [PATCH v2 0/3] i3c: dw: Support " Alexandre Belloni

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