[PATCH v5 4/4] media: ox05b1s: Add support for Omnivision OS08A20 raw sensor

[Mirela Rabulea <mirela.rabulea@nxp.com>]

This is an 8 megapixel raw10/raw12 sensor with HDR capabilities.
HDR mode control is supported, with one HDR mode: staggered HDR
with 2 exposures on separate virtual channels. However, for now,
only one exposure (VC 0) is accessible via get_frame_desc.

Supported resolutions:
   - 1920 x 1080 SBGGR10 (@60fps with no HDR)
   - 3840 x 2160 SBGGR12 (@30fps with no HDR)
   - 3840 x 2160 SBGGR10 (@30fps with no HDR)

When HDR mode is enabled, fps drops to half.

Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
---
Changes in v5:
	- Use cci_reg_sequence and CCI_REG8/16/24 macros all over (remove ox05b1s_reg).
	- Use cci_update_bits instead of regmap_update_bits
	- Go back to previous vts/hts settings for os08a20 1080p mode (changed in a
	previous version to get exactly 60 fps for this mode), instead restore
	another pll register that was removed, also in an earlier cleanup, in the end
	fps remains at 60 fps.
	- Also restore 0x3797 register setting, long to short distance mode due to
	regression, dark frames without it
	- Add back the commas after the last field of a structure (except for sentinels)
	- Add back some registers in the initial configuration lists that were
	cleaned up in v2 and later on found it was causing various problems
		BLC_CTRL08 and BLC_CTRL09 - washed out image in os08a20 1080p mode
		0x305 - image flickering and distortion only on some os08a20 sensors
		0x4050(zl_start), 0x4051(zl_end) - distorted colors on some OS08A20 sensors
	- Add define for OS08A20_CHIP_ID
	- Switch back to BGGR, until generic raw formats are merged
	- Add t1+t2 timing info for os08a20
	- Fix "bining" typo
	- Fix os08a20 4k 12bit HDR mode, only first frames were captured correctly for
	both VC0 and VC1). Use the same HTS and VTS values as for 4k 10bit mode, which works
	well even with HDR enabled
	- Get the number of MIPI data lanes from DT, since this is a board configuration property,
	and program the sensor registers accordingly, before streaming. Restrict to 4 datalanes for now,
	as not all modes are possible with 2 datalanes, at current data rates.
	- Do not hardcode one link_frequency, add one per mode
Changes in v4:
	Switch to Y media bus codes. The CFA pattern control will be implemented when patches get merged, or maybe separatelly as RFC?
	Add pixel_rate member to mode struct, remove fps member. We do not have information how to calculate the pixel rate from the PLL parameters that can be made public.
	Use register macros for the registers that are documented. User register group macros, where individual registers are not documented
	Constify more structs
	Remove some unneded ending commas after a terminator
	Fix a seeries of smatch warnings like: warning: symbol 'os08a20_init_setting_common' was not declared. Should it be static?
	Shorten some more lines to 80 columns

Changes in v3:
	Don't hardcode timing registers: remove timing registers x_output_size/y_output_size from register configuration list, add them to ox05b1s_apply_current_mode
	Remove HTS,VTS from register config list as they are written by HBLANK and VBLANK controls through __v4l2_ctrl_handler_setup
	Use const for os08a20_supported_modes	
	os08a20 register config cleaning (remove all registers that were at their default value, and more, keep only what seems mandatory to be able to stream)
	Let the 4k 10bit mode by default without hdr, all 3 modes are now by default without hdr, staggered hdr may be enabled via v4l2-ctl for any of them.
	Separate the 10/12 bit register settings into separate lists: os08a20_init_setting_10bit, os08a20_init_setting_12bit
	Update commit description: rearrange supported resolutions and remove 1 duplicate line, state HDR limitation
	Increase a bit the default vts for 1080p, to get exactly 60fps, it was 62.61
	Use regmap_update_bits() directly and remove ox05b1s_regmap_update_bits()

Changes in v2:
	Add spaces inside brackets, wrap lines to 80
	Remove some redundant initialization
	Use a loop in os08a20_enable_staggered_hdr/os08a20_disable_staggered_hdr, for that, add a register settings array for HDR enabling/disabling
	Make "sizes" a pointer
	Remove mode headers, add supported modes in the dedicated c file, ox05b1s_modes.c 
	Refactor register lists, for os08a20 use a common list for all modes, and also specific lists per mode

 drivers/media/i2c/ox05b1s/ox05b1s.h       |   4 +
 drivers/media/i2c/ox05b1s/ox05b1s_mipi.c  | 214 +++++++++++++++++++++-
 drivers/media/i2c/ox05b1s/ox05b1s_modes.c | 136 ++++++++++++++
 3 files changed, 353 insertions(+), 1 deletion(-)

diff --git a/drivers/media/i2c/ox05b1s/ox05b1s.h b/drivers/media/i2c/ox05b1s/ox05b1s.h
index f00ee1f2e78b..c4d3d1f435bf 100644
--- a/drivers/media/i2c/ox05b1s/ox05b1s.h
+++ b/drivers/media/i2c/ox05b1s/ox05b1s.h
@@ -14,6 +14,10 @@ struct ox05b1s_reglist {
 	unsigned int count;
 };
 
+extern const struct ox05b1s_reglist os08a20_reglist_4k_10b[];
+extern const struct ox05b1s_reglist os08a20_reglist_4k_12b[];
+extern const struct ox05b1s_reglist os08a20_reglist_1080p_10b[];
+
 extern const struct ox05b1s_reglist ox05b1s_reglist_2592x1944[];
 
 #endif /* OX05B1S_H */
diff --git a/drivers/media/i2c/ox05b1s/ox05b1s_mipi.c b/drivers/media/i2c/ox05b1s/ox05b1s_mipi.c
index 45d38dc836e6..d2ddda62e095 100644
--- a/drivers/media/i2c/ox05b1s/ox05b1s_mipi.c
+++ b/drivers/media/i2c/ox05b1s/ox05b1s_mipi.c
@@ -22,6 +22,7 @@
 #define OX05B1S_SENS_PAD_SOURCE	0
 #define OX05B1S_SENS_PADS_NUM	1
 #define OX05B1S_CHIP_ID 0x580542
+#define OS08A20_CHIP_ID 0x530841
 
 #define OX05B1S_REG_SW_STB		CCI_REG8(0x0100)
 #define OX05B1S_REG_SW_RST		CCI_REG8(0x0103)
@@ -36,6 +37,8 @@
 #define OX05B1S_REG_X_OUTPUT_SIZE	CCI_REG16(0x3808)
 #define OX05B1S_REG_Y_OUTPUT_SIZE	CCI_REG16(0x380a)
 
+#define OS08A20_REG_MIPI_SC		CCI_REG8(0x3012)
+
 #define client_to_ox05b1s(client)\
 	container_of(i2c_get_clientdata(client), struct ox05b1s, subdev)
 
@@ -44,6 +47,7 @@ struct ox05b1s_sizes {
 	const struct v4l2_area *sizes;
 };
 
+struct ox05b1s;
 struct ox05b1s_plat_data {
 	char				name[20];
 	u32				chip_id;
@@ -56,6 +60,9 @@ struct ox05b1s_plat_data {
 	const struct ox05b1s_mode	*supported_modes;
 	u32				default_mode_index;
 	const struct ox05b1s_sizes	*supported_codes;
+	const char * const		*hdr_modes;
+	u32				hdr_modes_count;
+	int (*set_hdr_mode)(struct ox05b1s *sensor, u32 hdr_mode);
 };
 
 struct ox05b1s_ctrls {
@@ -66,6 +73,7 @@ struct ox05b1s_ctrls {
 	struct v4l2_ctrl *vblank;
 	struct v4l2_ctrl *gain;
 	struct v4l2_ctrl *exposure;
+	struct v4l2_ctrl *hdr_mode;
 };
 
 struct ox05b1s_mode {
@@ -107,6 +115,105 @@ struct ox05b1s {
 	u32 num_data_lanes; /* number of MIPI CSI-2 data lanes */
 };
 
+static const struct ox05b1s_mode os08a20_supported_modes[] = {
+	{
+		/* 1080p BGGR10, no hdr, 60fps
+		 * SA1_CLK=138MHz, link_freq=360MHz (720 Mbps/lane), 4 lanes
+		 * pixel_rate = 360M*2*4/10 = 288 MHz
+		 * hblank = HTS*pixel_rate/SA1_CLK - width = 1936*288M/138M - 1920 = 2120
+		 */
+		.index		= 0,
+		.width		= 1920,
+		.height		= 1080,
+		.code		= MEDIA_BUS_FMT_SBGGR10_1X10,
+		.bpp		= 10,
+		.vts		= 0x4a4,
+		.hts		= 0x790,
+		.exp		= 0x4a4 - 8,
+		.sa1_clk	= 138000000,
+		.link_freq	= 360000000,
+		.reg_data	= os08a20_reglist_1080p_10b,
+	},
+	{
+		/* 4k BGGR10, no hdr, 30fps
+		 * SA1_CLK=144MHz, link_freq=480MHz (960 Mbps/lane), 4 lanes
+		 * pixel_rate = 480M*2*4/10 = 384 MHz
+		 * hblank = HTS*pixel_rate/SA1_CLK - width = 2072*384M/144M - 3840 = 1685
+		 */
+		.index		= 1,
+		.width		= 3840,
+		.height		= 2160,
+		.code		= MEDIA_BUS_FMT_SBGGR10_1X10,
+		.bpp		= 10,
+		.vts		= 0x90a,
+		.hts		= 0x818,
+		.exp		= 0x90a - 8,
+		.sa1_clk	= 144000000,
+		.link_freq	= 480000000,
+		.reg_data	= os08a20_reglist_4k_10b,
+	},
+	{
+		/* 4k BGGR12, no hdr, 30fps
+		 * SA1_CLK=142MHz, link_freq=480MHz (960 Mbps/lane), 4 lanes
+		 * pixel_rate = 480M*2*4/12 = 320 MHz
+		 * hblank = HTS*pixel_rate/SA1_CLK - width = 2072*320M/142M - 3840 = 829
+		 */
+		.index		= 2,
+		.width		= 3840,
+		.height		= 2160,
+		.code		= MEDIA_BUS_FMT_SBGGR12_1X12,
+		.bpp		= 12,
+		.vts		= 0x90a,
+		.hts		= 0x818,
+		.exp		= 0x90a - 8,
+		.sa1_clk	= 142000000,
+		.link_freq	= 480000000,
+		.reg_data	= os08a20_reglist_4k_12b,
+	},
+	{
+		/* sentinel */
+	}
+};
+
+/* keep in sync with os08a20_supported_modes */
+static const struct v4l2_area os08a20_sbggr10_sizes[] = {
+	{
+		.width = 1920,
+		.height = 1080,
+	},
+	{
+		.width = 3840,
+		.height = 2160,
+	},
+	{
+		/* sentinel */
+	}
+};
+
+static const struct v4l2_area os08a20_sbggr12_sizes[] = {
+	{
+		.width = 3840,
+		.height = 2160,
+	},
+	{
+		/* sentinel */
+	}
+};
+
+static const struct ox05b1s_sizes os08a20_supported_codes[] = {
+	{
+		.code = MEDIA_BUS_FMT_SBGGR10_1X10,
+		.sizes = os08a20_sbggr10_sizes,
+	},
+	{
+		.code = MEDIA_BUS_FMT_SBGGR12_1X12,
+		.sizes = os08a20_sbggr12_sizes,
+	},
+	{
+		/* sentinel */
+	}
+};
+
 static const struct ox05b1s_mode ox05b1s_supported_modes[] = {
 	{
 		/* 5Mp GRBG10, 30fps
@@ -182,6 +289,7 @@ static int ox05b1s_power_on(struct ox05b1s *sensor)
 	/*
 	 * wait t1 + t2
 	 * t1 = 0.5 ms, t2 = 0.25 * XVCLK (6ms @24MHz) for OX05B1S
+	 * t1 = 5 ms, t2 = 8192 cycles (1.36 ms @6Mhz) for OS08A20
 	 */
 	fsleep(6500);
 
@@ -226,6 +334,58 @@ static int ox05b1s_runtime_resume(struct device *dev)
 	return ox05b1s_power_on(sensor);
 }
 
+static const char * const os08a20_hdr_modes[] = {
+	"NO HDR", /* No HDR, single exposure */
+	"HDR Staggered", /* Staggered HDR mode, 2 exposures on separate VC */
+};
+
+static const struct cci_reg_sequence os08a20_init_setting_hdr_en[] = {
+	{CCI_REG8(0x3661), BIT(0)}, /* CORE1[0] STG_HDR_ALIGN_EN */
+	{CCI_REG8(0x3821), BIT(5)}, /* FORMAT2[5] STG_HDR_EN */
+	{CCI_REG8(0x4813), BIT(3)}, /* MIPI_CTRL_13[3] */
+	{CCI_REG8(0x486e), BIT(2)}, /* MIPI_CTRL_6E[2] MIPI_VC_ENABLE */
+};
+
+static int os08a20_enable_staggered_hdr(struct ox05b1s *sensor)
+{
+	int ret = 0;
+
+	for (int i = 0; i < ARRAY_SIZE(os08a20_init_setting_hdr_en); i++) {
+		cci_update_bits(sensor->regmap,
+				os08a20_init_setting_hdr_en[i].reg,
+				os08a20_init_setting_hdr_en[i].val,
+				os08a20_init_setting_hdr_en[i].val, &ret);
+	}
+
+	return ret;
+}
+
+static int os08a20_disable_staggered_hdr(struct ox05b1s *sensor)
+{
+	int ret = 0;
+
+	for (int i = 0; i < ARRAY_SIZE(os08a20_init_setting_hdr_en); i++) {
+		cci_update_bits(sensor->regmap,
+				os08a20_init_setting_hdr_en[i].reg,
+				os08a20_init_setting_hdr_en[i].val,
+				0, &ret);
+	}
+
+	return ret;
+}
+
+static int os08a20_set_hdr_mode(struct ox05b1s *sensor, u32 hdr_mode)
+{
+	switch (hdr_mode) {
+	case 0:
+		return os08a20_disable_staggered_hdr(sensor);
+	case 1:
+		return os08a20_enable_staggered_hdr(sensor);
+	default:
+		return -EINVAL;
+	}
+}
+
 static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
 {
 	return &container_of(ctrl->handler, struct ox05b1s,
@@ -281,6 +441,12 @@ static int ox05b1s_s_ctrl(struct v4l2_ctrl *ctrl)
 		ret = cci_write(sensor->regmap, OX05B1S_REG_EXPOSURE,
 				ctrl->val, NULL);
 		break;
+	case V4L2_CID_HDR_SENSOR_MODE:
+		if (sensor->model->set_hdr_mode)
+			ret = sensor->model->set_hdr_mode(sensor, ctrl->val);
+		else
+			ret = -EINVAL;
+		break;
 	default:
 		ret = -EINVAL;
 		break;
@@ -302,6 +468,8 @@ static const struct v4l2_ctrl_ops ox05b1s_ctrl_ops = {
  */
 static const s64 ox05b1s_csi2_link_freqs[] = {
 	320000000, /* OX05B1S 2592x1944 10b @30fps:  640 Mbps/lane */
+	360000000, /* OS08A20 1080p 10b @60fps:       720 Mbps/lane */
+	480000000, /* OS08A20 4K 10b @30fps, 4K 12b:  960 Mbps/lane */
 };
 
 static int ox05b1s_init_controls(struct ox05b1s *sensor)
@@ -356,6 +524,13 @@ static int ox05b1s_init_controls(struct ox05b1s *sensor)
 	ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
 					0, 0xFFFF, 1, 0x80);
 
+	if (sensor->model->hdr_modes)
+		ctrls->hdr_mode = v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_HDR_SENSOR_MODE,
+							       sensor->model->hdr_modes_count - 1,
+								0, 0, sensor->model->hdr_modes);
+	else
+		ctrls->hdr_mode = NULL;
+
 	if (hdl->error) {
 		ret = hdl->error;
 		goto free_ctrls;
@@ -565,6 +740,9 @@ static int ox05b1s_apply_mipi_num_lanes(struct ox05b1s *sensor)
 	u32 reg;
 
 	switch (sensor->model->chip_id) {
+	case OS08A20_CHIP_ID:
+		reg = OS08A20_REG_MIPI_SC;
+		break;
 	case OX05B1S_CHIP_ID:
 		reg = OX05B1S_REG_SC_CMMN_REG10;
 		break;
@@ -572,7 +750,7 @@ static int ox05b1s_apply_mipi_num_lanes(struct ox05b1s *sensor)
 		return -EINVAL;
 	}
 
-	/* Update only the lane count field */
+	/* Update only the lane count field, same position for OX05B1S/OS08A20 */
 	return cci_update_bits(sensor->regmap, reg,
 			       OX05B1S_MIPI_NLANE_MASK,
 			       sensor->num_data_lanes << OX05B1S_MIPI_NLANE_SHIFT,
@@ -709,7 +887,10 @@ static u8 ox05b1s_code2dt(const u32 code)
 {
 	switch (code) {
 	case MEDIA_BUS_FMT_SGRBG10_1X10:
+	case MEDIA_BUS_FMT_SBGGR10_1X10:
 		return MIPI_CSI2_DT_RAW10;
+	case MEDIA_BUS_FMT_SBGGR12_1X12:
+		return MIPI_CSI2_DT_RAW12;
 	default:
 		return MIPI_CSI2_DT_RAW10;
 	}
@@ -729,6 +910,10 @@ static int ox05b1s_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
 	fd->entry[0].pixelcode = sensor->mode->code;
 	mutex_unlock(&sensor->lock);
 
+	/*
+	 * expose only VC0, to be updated to expose also VC1 (for hdr mode)
+	 * when it will be possible to add routes and internal pads
+	 */
 	fd->entry[0].bus.csi2.vc = 0;
 	fd->entry[0].bus.csi2.dt = ox05b1s_code2dt(fd->entry[0].pixelcode);
 
@@ -874,6 +1059,9 @@ static int ox05b1s_read_chip_id(struct ox05b1s *sensor)
 	}
 
 	switch (chip_id) {
+	case OS08A20_CHIP_ID:
+		camera_name = "os08a20";
+		break;
 	case OX05B1S_CHIP_ID:
 		camera_name = "ox05b1s";
 		break;
@@ -1078,6 +1266,23 @@ static void ox05b1s_remove(struct i2c_client *client)
 static DEFINE_RUNTIME_DEV_PM_OPS(ox05b1s_pm_ops, ox05b1s_runtime_suspend,
 				 ox05b1s_runtime_resume, NULL);
 
+static const struct ox05b1s_plat_data os08a20_data = {
+	.name			= "os08a20",
+	.chip_id		= 0x530841,
+	.native_width		= 3872, /* 16 dummy + 3840 active + 16 dummy */
+	.native_height		= 2192, /* 16 dummy + 2160 active + 16 dummy */
+	.active_top		= 16,
+	.active_left		= 16,
+	.active_width		= 3840,
+	.active_height		= 2160,
+	.supported_modes	= os08a20_supported_modes,
+	.default_mode_index	= 0,
+	.supported_codes	= os08a20_supported_codes,
+	.hdr_modes		= os08a20_hdr_modes,
+	.hdr_modes_count	= ARRAY_SIZE(os08a20_hdr_modes),
+	.set_hdr_mode		= os08a20_set_hdr_mode,
+};
+
 static const struct ox05b1s_plat_data ox05b1s_data = {
 	.name			= "ox05b1s",
 	.chip_id		= 0x580542,
@@ -1090,9 +1295,16 @@ static const struct ox05b1s_plat_data ox05b1s_data = {
 	.supported_modes	= ox05b1s_supported_modes,
 	.default_mode_index	= 0,
 	.supported_codes	= ox05b1s_supported_codes,
+	.hdr_modes		= NULL,
+	.hdr_modes_count	= 0,
+	.set_hdr_mode		= NULL,
 };
 
 static const struct of_device_id ox05b1s_of_match[] = {
+	{
+		.compatible = "ovti,os08a20",
+		.data = &os08a20_data,
+	},
 	{
 		.compatible = "ovti,ox05b1s",
 		.data = &ox05b1s_data,
diff --git a/drivers/media/i2c/ox05b1s/ox05b1s_modes.c b/drivers/media/i2c/ox05b1s/ox05b1s_modes.c
index c7371418bbd0..e30851ecd94a 100644
--- a/drivers/media/i2c/ox05b1s/ox05b1s_modes.c
+++ b/drivers/media/i2c/ox05b1s/ox05b1s_modes.c
@@ -10,6 +10,142 @@
 #include <media/v4l2-cci.h>
 #include "ox05b1s.h"
 
+#define OS08A20_REG_PLL_CTRL_05		CCI_REG8(0x0305)
+#define OS08A20_REG_PLL_CTRL_25		CCI_REG8(0x0325)
+#define OS08A20_REG_MIPI_BIT_10_12	CCI_REG8(0x031e)
+/* Analog Control Registers 0x3600-0x3637 */
+#define OS08A20_REG_ANA_CTRL		CCI_REG8(0x3600)
+#define OS08A20_REG_CORE_0		CCI_REG8(0x3660)
+/* Sensor Timing Control Registers 0x3700-0x37ff */
+#define OS08A20_REG_SENSOR_TIMING_CTRL	CCI_REG8(0x3700)
+#define OS08A20_REG_L2S_MODE		CCI_REG8(0x3797)
+#define OS08A20_REG_X_ODD_INC		CCI_REG8(0x3814)
+#define OS08A20_REG_Y_ODD_INC		CCI_REG8(0x3816)
+#define OS08A20_REG_FORMAT1		CCI_REG8(0x3820)
+#define OS08A20_REG_FORMAT2		CCI_REG8(0x3821)
+#define OS08A20_REG_BLC_CTRL08		CCI_REG8(0x4008)
+#define OS08A20_REG_BLC_CTRL09		CCI_REG8(0x4009)
+#define OS08A20_REG_BLC_CTRL50		CCI_REG8(0x4050)
+#define OS08A20_REG_BLC_CTRL51		CCI_REG8(0x4051)
+#define OS08A20_REG_PCLK_PERIOD		CCI_REG8(0x4837)
+#define OS08A20_REG_ISP_CTRL_1		CCI_REG8(0x5001)
+#define OS08A20_REG_ISP_CTRL_5		CCI_REG8(0x5005)
+
+/* Common register configuration for Omnivision OS08A20 raw camera */
+static const struct cci_reg_sequence os08a20_init_setting_common[] = {
+	{OS08A20_REG_ANA_CTRL + 0x05, 0x50},
+	{OS08A20_REG_ANA_CTRL + 0x10, 0x39},
+	{OS08A20_REG_SENSOR_TIMING_CTRL + 0x5e, 0x0b},
+	{OS08A20_REG_L2S_MODE, 0x04},
+	{OS08A20_REG_BLC_CTRL08, 0x02},
+	{OS08A20_REG_BLC_CTRL09, 0x0d},
+	{OS08A20_REG_BLC_CTRL50, 0x00},
+	{OS08A20_REG_BLC_CTRL51, 0x01},
+	{OS08A20_REG_ISP_CTRL_1, 0x42},
+	{OS08A20_REG_ISP_CTRL_5, 0x00},
+};
+
+/* Common register configuration for Omnivision OS08A20 10 bit */
+static const struct cci_reg_sequence os08a20_init_setting_10bit[] = {
+	{OS08A20_REG_MIPI_BIT_10_12, 0x09},
+	{OS08A20_REG_ANA_CTRL + 0x09, 0xb5},
+	{OS08A20_REG_CORE_0, 0x43},
+	{OS08A20_REG_SENSOR_TIMING_CTRL + 0x06, 0x35},
+	{CCI_REG24(0x3709), 0x490098},
+};
+
+/* Common register configuration for Omnivision OS08A20 12 bit */
+static const struct cci_reg_sequence os08a20_init_setting_12bit[] = {
+	{OS08A20_REG_MIPI_BIT_10_12, 0x0a},
+	{OS08A20_REG_ANA_CTRL + 0x09, 0xdb},
+	{OS08A20_REG_CORE_0, 0xd3},
+	{OS08A20_REG_SENSOR_TIMING_CTRL + 0x06, 0x6a},
+	{CCI_REG24(0x3709), 0x480130},
+};
+
+/* Mode specific register configurations for Omnivision OS08A20 raw camera */
+
+/* OS08A20 3840 x 2160 @30fps BGGR10 */
+static const struct cci_reg_sequence os08a20_init_setting_4k_10b[] = {
+	{OS08A20_REG_PLL_CTRL_05, 0x3c},
+	{OS08A20_REG_FORMAT2, 0x04}, /* mirror */
+	{OS08A20_REG_PCLK_PERIOD, 0x10},
+};
+
+/* OS08A20 3840 x 2160 @30fps BGGR12 */
+static const struct cci_reg_sequence os08a20_init_setting_4k_12b[] = {
+	{OS08A20_REG_PLL_CTRL_05, 0x3c},
+	{OS08A20_REG_PLL_CTRL_25, 0x47},
+	{OS08A20_REG_FORMAT2, 0x04}, /* mirror */
+	{OS08A20_REG_PCLK_PERIOD, 0x10},
+};
+
+/* OS08A20 1920 x 1080 @60fps BGGR10 */
+static const struct cci_reg_sequence os08a20_init_setting_1080p_10b[] = {
+	{OS08A20_REG_PLL_CTRL_05, 0x2d},
+	{OS08A20_REG_PLL_CTRL_25, 0x45},
+	{OS08A20_REG_X_ODD_INC, 0x03},
+	{OS08A20_REG_Y_ODD_INC, 0x03},
+	{OS08A20_REG_FORMAT1, 0x01}, /* vertical binning */
+	{OS08A20_REG_FORMAT2, 0x05}, /* mirror, horizontal binning */
+	{OS08A20_REG_BLC_CTRL09, 0x05},
+	{OS08A20_REG_PCLK_PERIOD, 0x16},
+};
+
+const struct ox05b1s_reglist os08a20_reglist_4k_10b[] = {
+	{
+		.regs = os08a20_init_setting_common,
+		.count = ARRAY_SIZE(os08a20_init_setting_common),
+	},
+	{
+		.regs = os08a20_init_setting_10bit,
+		.count = ARRAY_SIZE(os08a20_init_setting_10bit),
+	},
+	{
+		.regs = os08a20_init_setting_4k_10b,
+		.count = ARRAY_SIZE(os08a20_init_setting_4k_10b),
+	},
+	{
+		/* sentinel */
+	}
+};
+
+const struct ox05b1s_reglist os08a20_reglist_4k_12b[] = {
+	{
+		.regs = os08a20_init_setting_common,
+		.count = ARRAY_SIZE(os08a20_init_setting_common),
+	},
+	{
+		.regs = os08a20_init_setting_12bit,
+		.count = ARRAY_SIZE(os08a20_init_setting_12bit),
+	},
+	{
+		.regs = os08a20_init_setting_4k_12b,
+		.count = ARRAY_SIZE(os08a20_init_setting_4k_12b),
+	},
+	{
+		/* sentinel */
+	}
+};
+
+const struct ox05b1s_reglist os08a20_reglist_1080p_10b[] = {
+	{
+		.regs = os08a20_init_setting_common,
+		.count = ARRAY_SIZE(os08a20_init_setting_common),
+	},
+	{
+		.regs = os08a20_init_setting_10bit,
+		.count = ARRAY_SIZE(os08a20_init_setting_10bit),
+	},
+	{
+		.regs = os08a20_init_setting_1080p_10b,
+		.count = ARRAY_SIZE(os08a20_init_setting_1080p_10b),
+	},
+	{
+		/* sentinel */
+	}
+};
+
 #define OX05B1S_REG_PLL1_CTRL_REG07	CCI_REG8(0x0307)
 #define OX05B1S_REG_PLL3_CTRL_REG4A	CCI_REG8(0x034a)
 #define OX05B1S_REG_PLL_MONITOR_REG0B	CCI_REG8(0x040b)
-- 
2.43.0