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Mon, 05 Oct 2026 15:40:46 -0700 (PDT) From: Coia Prant To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Lin , David Heidelberg , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Coia Prant Subject: [PATCH v10 2/2] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port Date: Tue, 6 Oct 2026 06:40:08 +0800 Message-ID: <20261005224008.1140250-3-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261005224008.1140250-1-coiaprant@gmail.com> References: <20261005224008.1140250-1-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Ariaboard Photonicat has a Motorcomm YT8521SC Gigabit Ethernet PHY connected to GMAC0 via XPCS SGMII. Enable the necessary nodes to make this port functional. Add rockchip,sgmii-mac-sel = <0> to the already enabled combphy2, to route the SGMII interface to GMAC0. RK3568 has three Combo PHYs that can carry SGMII; which one is wired to the XPCS is a board-level choice, and Photonicat uses combphy2. Enable the xpcs node and its port 0 sub-node, referencing combphy2 as the SerDes PHY. Add the mdio0 node with the YT8521SC PHY at address 3, including its reset GPIO and LED configuration. Also add LED configuration for the existing RGMII PHY on mdio1 for consistency. Signed-off-by: Coia Prant --- .../boot/dts/rockchip/rk3568-photonicat.dts | 74 ++++++++++++++++++- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts index 58c1052ba8ef3..fdaa4a2a4328b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts @@ -3,6 +3,7 @@ /dts-v1/; #include +#include #include #include #include "rk3568.dtsi" @@ -241,6 +242,7 @@ &combphy1 { }; &combphy2 { + rockchip,sgmii-mac-sel = <0>; status = "okay"; }; @@ -260,9 +262,18 @@ &cpu3 { cpu-supply = <&vdd_cpu>; }; -/* Motorcomm YT8521SC LAN port (require SGMII) */ +/* Motorcomm YT8521SC LAN port */ &gmac0 { - status = "disabled"; + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>; + assigned-clock-parents = <&clk_gmac0_xpcs_mii>; + managed = "in-band-status"; + pcs-handle = <&xpcs_mii0>; + phy-handle = <&sgmii_phy>; + phy-mode = "sgmii"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim>; + status = "okay"; }; /* Motorcomm YT8521SC WAN port */ @@ -341,6 +352,36 @@ &i2s0_8ch { status = "okay"; }; +&mdio0 { + sgmii_phy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + max-speed = <1000>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; +}; + &mdio1 { rgmii_phy: ethernet-phy@3 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -350,6 +391,25 @@ rgmii_phy: ethernet-phy@3 { reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; rx-internal-delay-ps = <1500>; tx-internal-delay-ps = <1500>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_WAN; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_WAN; + default-state = "keep"; + }; + }; }; }; @@ -586,3 +646,13 @@ &xin32k { pinctrl-names = "default"; pinctrl-0 = <&clk32k_out1>; }; + +&xpcs { + phys = <&combphy2 PHY_TYPE_SGMII>; + phy-names = "serdes"; + status = "okay"; +}; + +&xpcs_mii0 { + status = "okay"; +}; -- 2.47.3