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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-15d85781d49sm4017403c88.16.2026.10.05.22.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Oct 2026 22:29:51 -0700 (PDT) From: Varadarajan Narayanan Date: Tue, 06 Oct 2026 10:59:19 +0530 Subject: [PATCH v5 5/6] phy: qcom: snps-femto-v2: Move PHY init registers to config tables Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261006-phy-v5-5-cbe9330a6449@oss.qualcomm.com> References: <20261006-phy-v5-0-cbe9330a6449@oss.qualcomm.com> In-Reply-To: <20261006-phy-v5-0-cbe9330a6449@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Manu Gautam , Stephen Boyd , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=HtPjiETS c=1 sm=1 tr=0 ts=6ac48751 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=dpbSYRCFOxhwq305YcMA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-GUID: OIoRxXjWflFAYA_YCkafx1LSgYnUPPcb X-Proofpoint-ORIG-GUID: OIoRxXjWflFAYA_YCkafx1LSgYnUPPcb X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA2MDAyMSBTYWx0ZWRfXympP4uwpkcFh oQBlZKZ66BQY42bQYtGzn0s8OBvT2e99ZdQ4089Z3FoE+2zf6JUmbC4KtBB1fR5VIOqW9EOFZaR pfRnMh6PcNFwn9gKSeX5ZZ5Pheq/sDY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA2MDAyMSBTYWx0ZWRfX293ZHbDccoaU 11MnpRS7Hx6+0cCHWenefbtSZ2t9173uhFc0YYgAH74+zimClxRsCuqK3sbQvMGm48gSyOqn06Q qV9rtUofpZhlHwNmKbgJXzH6CLYq4xAFmhvR0vrbLL+caec1cZahseMIw1AYYonJZRQw0/zJsuB lJARiOJQ/1gfJeznxyeYXr8fMiThFYK4G9UXgFSce3zqEJd7p9jRLXn/ts7bEAdyeDOEoItGhXL dzN5w8Ai/XRjBNifcyz99bVlWfQ8UMSup4DIe+bNPjR9NUgD31lbt6osCutsgzQkAdPW5hyXDa1 31R2viKwP3wYlr8RALJ1Rfn9g9BT9E23ank4Z90uUpuNcLKUvVRbGGraQB7FDtTkEQEPwSSPBYX 7GqvmQCnCYODFPjuEH9vqcGcpnnfNxwJO1cJU4rbY9rNpsgZ/DOFKfg/feCICHWPtw+k0smUlOT ffy2AQKUnefQyFNvbWw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-06_01,2026-10-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610060021 The driver currently programs the common PHY register sequence directly in qcom_snps_hsphy_init(), with the fixed register writes split around the override parameter handling. This makes it hard to support SoCs that need a different sequence or different values. Move the fixed pre- and post-override register programming into per- compatible configuration tables, and keep the 7 nm override parameters in the same match-data structure. This allows the driver to share the common sequence while adding SoC-specific sequences for future platforms such as IPQ9650. Signed-off-by: Varadarajan Narayanan --- drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 129 +++++++++++++++++--------- 1 file changed, 83 insertions(+), 46 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c index 0ead37c0dcfd..2e37b39dabba 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -104,6 +104,20 @@ struct phy_override_seq { u8 mask; }; +struct phy_reg_config { + u32 offset; + u32 mask; + u32 val; +}; + +struct phy_config_data { + const struct phy_reg_config *pre_tuning; + const struct override_param_map *override; + const struct phy_reg_config *post_tuning; + const u32 num_pre_tuning; + const u32 num_post_tuning; +}; + #define NUM_HSPHY_TUNING_PARAMS (9) /** @@ -383,13 +397,39 @@ static const struct override_param_map sc7280_snps_7nm_phy[] = { {}, }; +static const struct phy_reg_config hs_5nm_phy_pre_tuning[] = { + { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, UTMI_PHY_CMN_CTRL_OVERRIDE_EN }, + { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, POR }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, FSEL_MASK, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, PLLBTUNE, PLLBTUNE }, + { USB2_PHY_USB_PHY_REFCLK_CTRL, REFCLK_SEL_MASK, REFCLK_SEL_DEFAULT }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, VBUSVLDEXTSEL0, VBUSVLDEXTSEL0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL1, VBUSVLDEXT0, VBUSVLDEXT0 }, +}; + +static const struct phy_reg_config hs_5nm_phy_post_tuning[] = { + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, VREGBYPASS, VREGBYPASS }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N }, + { USB2_PHY_USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0 }, + { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 0 }, + { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0 }, +}; + static int qcom_snps_hsphy_init(struct phy *phy) { struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); + const struct phy_config_data *data; int ret, i; dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__); + data = of_device_get_match_data(hsphy->dev); + if (!data) + return -ENODEV; + ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); if (ret) return ret; @@ -414,24 +454,11 @@ static int qcom_snps_hsphy_init(struct phy *phy) goto disable_clks; } - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, - UTMI_PHY_CMN_CTRL_OVERRIDE_EN, - UTMI_PHY_CMN_CTRL_OVERRIDE_EN); - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, - POR, POR); - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, - FSEL_MASK, 0); - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, - PLLBTUNE, PLLBTUNE); - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL, - REFCLK_SEL_MASK, REFCLK_SEL_DEFAULT); - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, - VBUSVLDEXTSEL0, VBUSVLDEXTSEL0); - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, - VBUSVLDEXT0, VBUSVLDEXT0); + for (i = 0; i < data->num_pre_tuning; i++) + qcom_snps_hsphy_write_mask(hsphy->base, + data->pre_tuning[i].offset, + data->pre_tuning[i].mask, + data->pre_tuning[i].val); for (i = 0; i < ARRAY_SIZE(hsphy->update_seq_cfg); i++) { if (hsphy->update_seq_cfg[i].need_update) @@ -441,28 +468,11 @@ static int qcom_snps_hsphy_init(struct phy *phy) hsphy->update_seq_cfg[i].value); } - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, - VREGBYPASS, VREGBYPASS); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, - USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, - USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0, - SLEEPM, SLEEPM); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, - SIDDQ, 0); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, - POR, 0); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, - USB2_SUSPEND_N_SEL, 0); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, - UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); + for (i = 0; i < data->num_post_tuning; i++) + qcom_snps_hsphy_write_mask(hsphy->base, + data->post_tuning[i].offset, + data->post_tuning[i].mask, + data->post_tuning[i].val); hsphy->phy_initialized = true; @@ -495,14 +505,38 @@ static const struct phy_ops qcom_snps_hsphy_gen_ops = { .owner = THIS_MODULE, }; +static const struct phy_config_data hs_5nm_phy = { + .pre_tuning = hs_5nm_phy_pre_tuning, + .num_pre_tuning = ARRAY_SIZE(hs_5nm_phy_pre_tuning), + .post_tuning = hs_5nm_phy_post_tuning, + .num_post_tuning = ARRAY_SIZE(hs_5nm_phy_post_tuning), +}; + +static const struct phy_config_data hs_7nm_phy = { + .pre_tuning = hs_5nm_phy_pre_tuning, + .num_pre_tuning = ARRAY_SIZE(hs_5nm_phy_pre_tuning), + .override = sc7280_snps_7nm_phy, + .post_tuning = hs_5nm_phy_post_tuning, + .num_post_tuning = ARRAY_SIZE(hs_5nm_phy_post_tuning), +}; + static const struct of_device_id qcom_snps_hsphy_of_match_table[] = { - { .compatible = "qcom,sm8150-usb-hs-phy", }, - { .compatible = "qcom,usb-snps-hs-5nm-phy", }, + { + .compatible = "qcom,sm8150-usb-hs-phy", + .data = &hs_5nm_phy, + }, + { + .compatible = "qcom,usb-snps-hs-5nm-phy", + .data = &hs_5nm_phy, + }, { .compatible = "qcom,usb-snps-hs-7nm-phy", - .data = &sc7280_snps_7nm_phy, + .data = &hs_7nm_phy, + }, + { + .compatible = "qcom,usb-snps-femto-v2-phy", + .data = &hs_5nm_phy, }, - { .compatible = "qcom,usb-snps-femto-v2-phy", }, { } }; MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table); @@ -541,11 +575,14 @@ static void qcom_snps_hsphy_read_override_param_seq(struct device *dev) s32 val; int ret, i; struct qcom_snps_hsphy *hsphy; - const struct override_param_map *cfg = of_device_get_match_data(dev); + const struct phy_config_data *data = of_device_get_match_data(dev); + const struct override_param_map *cfg; - if (!cfg) + if (!data || !data->override) return; + cfg = data->override; + hsphy = dev_get_drvdata(dev); for (i = 0; cfg[i].prop_name != NULL; i++) { -- 2.34.1