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([179.179.237.181]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3515af170c5sm717764eec.11.2026.10.06.12.31.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Oct 2026 12:31:11 -0700 (PDT) From: Vinicius Pedrosa To: Andre Przywara , linux-serial@vger.kernel.org Cc: gregkh@linuxfoundation.org, jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andriy.shevchenko@linux.intel.com, ilpo.jarvinen@linux.intel.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Enzo Adriano Subject: Re: [PATCH 3/3] serial: 8250_dw: Add Allwinner A733 UART Date: Tue, 6 Oct 2026 16:30:46 -0300 Message-ID: <20261006193046.540252-1-vinicius.eduardo.pedrosa@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <603b4f40-2a60-4bc5-8b98-ada7a52fead9@arm.com> References: <20261005172538.398522-1-vinicius.eduardo.pedrosa@gmail.com> <20261005172538.398522-4-vinicius.eduardo.pedrosa@gmail.com> <603b4f40-2a60-4bc5-8b98-ada7a52fead9@arm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Andre, On 10/6/26 14:16, Andre Przywara wrote: > So isn't that a bug somewhere else then? Why would it gate the clock to > set the rate? I think the bug is in dw8250_set_termios(). The gate comes from 4e26b134bd17 (2014, replacing the Baytrail hook) and runs on every termios change that reaches the driver, with nothing draining the port first. On LPSS the UART's clock ends in a gate on bit 31, the divider update bit, so I'd guess the disable/enable pair is how a new rate gets latched there. On the A733 the DT hands over only the bus gate, so that is what gets pulsed. > And what is your use case here, exactly? Do you reconfigure the baud > rate while characters are incoming? No baud change. I toggled only CLOCAL with TCSANOW, 300 times while the console printed 3000 lines. With the gate alone every run lost 12 to 18 lines (3 runs). With round_rate and set_rate but no gate, all 3 were clean. A CSTOPB toggle splits the same way over 6 runs each. > So can you just expose CLK_APB1 as the baud rate clock in the DT? On the A733 the UARTs aren't on APB1. They sit on APB_UART (0x538), shared by the seven UARTs. I tried it as baudclk with the bus gate as apb_pclk and the console was garbage. The driver asks for 16 x baud and the CCU rounds down, so 115200 gets RC16M/9 = 1777778 and divisor 1 gives 111111 baud. 24M/13 is just above the target, so it isn't picked. ccu-sun6i-rtc lists RC16M at 30% accuracy anyway. It's also shared: 01569a29af76 removed the clock notifier in 7.2, so a port that re-rates APB_UART would leave the other six with stale divisors. For v2 I'd drop SKIP_SET_RATE for the A733 and only gate and set the rate when clk_round_rate() differs from clk_get_rate(). By my reading the branch is never taken here, and that kernel was clean in all 13 runs. H6, H616 and A523 pass only a bus gate too, so they likely see the same thing, but I can't test them. Would you rather drop the gate altogether? I kept it because I can't test LPSS. Thanks, Vinicius