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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1615f1ac8c5sm7374730c88.2.2026.10.06.23.50.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Oct 2026 23:51:04 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 07 Oct 2026 12:20:45 +0530 Subject: [PATCH 2/4] clk: qcom: clk-alpha-pll: Skip Zonda PLL configuration if already enabled Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261007-ipq9650_apss_clk-v1-2-fd4c2b3cbdea@oss.qualcomm.com> References: <20261007-ipq9650_apss_clk-v1-0-fd4c2b3cbdea@oss.qualcomm.com> In-Reply-To: <20261007-ipq9650_apss_clk-v1-0-fd4c2b3cbdea@oss.qualcomm.com> To: Georgi Djakov , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.15.2 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDAyNyBTYWx0ZWRfX+n7djOlmq4Mv eCYDdRP1p7JatxXb+7b1/j81tAQ6ysUnP1OKQ/Ybe8eDcBTCeTszzsWgOFY8QM4OrGL2YnsFXbM XVrzS7bRb9vt1/Zf7YH238F0/OnKeeM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDAyNyBTYWx0ZWRfX5bUhdZsBZFyG EG+Gu8t41lpMqzuTWHsPc3lbnf9s6AoFh1ljWmkj05XzFYPdo7jnvUhdJDT5CrNFFD4GaSFtA1O GptD2Ezq9hVIeLzvm6QHG3WQdRON6wFMfMcKvp+lGN48sMOc0pUv7nPzWFZVcxCdct2roJsOHU1 5uC7omxANBIblkKk9GZaSOdWAJ+qGua8OMSPz/yDCB4rnPW4g0JiSK1AtrH8R7FDg4//GNx8vVB wdmPwgIV70lwW+8QircBKs5Wz/ZUmVFBqHVHxrvOxmu/RJJe6bmlANQeKAKlMyywzj7mYCHeGaM q7O4evZjhM2Mg0RNxnQDnkb7uclbUbuC1eHjsIHA3fXF6FuXjGd0AKyf0H35COOcsoPQOLQuTkm KoOxOhm/sTCc21P/8WzAVOuvtgM6txgHGB4G7xPVNmAGKhKm6KQXxHPV76NGqf0SfDavN0IBpEJ hCB3jyp0aqh0AH7DTcQ== X-Proofpoint-ORIG-GUID: 7yREhjB7Nx2YLrGVJnA8_3sFFT8YeQU0 X-Authority-Analysis: v=2.4 cv=T5EZ3PKQ c=1 sm=1 tr=0 ts=6ac5ebd9 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=HvQ8q7LFvqEYzEKEMhkA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-GUID: 7yREhjB7Nx2YLrGVJnA8_3sFFT8YeQU0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_02,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 clxscore=1015 bulkscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070027 On IPQ9650, the bootloader configures and enables the APSS Zonda PLL that provide the clocks for the A55 CPU cores and L3 interconnect. When the APSS clock driver probes, it attempts to reconfigure the already running PLLs. As part of the reconfiguration sequence, the PLL output is disabled and the PLL is placed into standby before being re-enabled. Since the CPUs are actively clocked from these PLLs, removing the clock during this window causes the system to hang. Avoid reconfiguring PLLs that are already enabled and return early, similar to clk_trion_pll_configure(). Signed-off-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/clk-alpha-pll.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 60173b076cc5..3641b2da92cd 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -2162,6 +2162,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { + /* Check if PLL is already enabled */ + if (trion_pll_is_enabled(pll, regmap)) + return; + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); -- 2.34.1