From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from twmbx01.aspeedtech.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE815456E11; Thu, 8 Oct 2026 11:28:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791458920; cv=none; b=ib00LWhj/jvNwzVDSxE80uX44u3oNudwLzwtPZmOuaqfZnaTJSU670zJ19lYIZdD8TPICCJL59R9MuMqg2XYOAGq53ttBUQaJvAsprltWyH1SsTuypBa2qYvAKgxFIOeSVIcSRej6e/5XAtCYdna4HyPfS9AkVqVp4HoCaU9ISA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791458920; c=relaxed/simple; bh=R1Rp45+kmKh9eM16JpYNajIX3lEUCLAV021oQUooi3w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=qvMMsfnCbY8NrSDSJ/T8AU+wxUMnY+hv6U9lvUMLH6jxBKM8ypc5Tw06BpD+jZUm+mBJhbhyt5wB1RRBWg/EiGAHAd5WYNGAy+byWhsbG1SUhp50YPOD0cZ1u5kqd5AlOj95Uysenipr4YISb0QXDnn8AvQpCV5x2I5FqYSgVtU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 8 Oct 2026 19:28:28 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 8 Oct 2026 19:28:28 +0800 From: Jacky Chou Date: Thu, 8 Oct 2026 19:28:19 +0800 Subject: [PATCH 1/3] dt-bindings: phy: aspeed: Add ASPEED PCIe PHY Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20261008-aspeed_pcie_phy-v1-1-96764937aef0@aspeedtech.com> References: <20261008-aspeed_pcie_phy-v1-0-96764937aef0@aspeedtech.com> In-Reply-To: <20261008-aspeed_pcie_phy-v1-0-96764937aef0@aspeedtech.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Manivannan Sadhasivam , Ryan Chen , Billy Tsai CC: , , , , , Jacky Chou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791458908; l=1816; i=jacky_chou@aspeedtech.com; s=20251031; h=from:subject:message-id; bh=R1Rp45+kmKh9eM16JpYNajIX3lEUCLAV021oQUooi3w=; b=QtvZBxEegbrYy4Tja19fXhxOY7/V57v5Nz2LD/pFCWnOWiUGwKQFAr0KYu1YOiqpnntDbDZJ3 Ma+fzCLojZEA0HqMt0u3AENCL8onaoZIpNyQfxhwXgOE4EnZ8YTEny3 X-Developer-Key: i=jacky_chou@aspeedtech.com; a=ed25519; pk=8XBx7KFM1drEsfCXTH9QC2lbMlGU4XwJTA6Jt9Mabdo= Introduce device-binding for ASPEED AST2600/2700 PCIe PHY. The PHY provides the physical layer used by the PCIe controller when operating in root complex mode. Describe the compatible strings, register range, clocks and phy-cells value required by the PHY provider. Signed-off-by: Jacky Chou --- .../bindings/phy/aspeed,ast2600-pcie-phy.yaml | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml new file mode 100644 index 000000000000..686b2e3d9457 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/aspeed,ast2600-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED PCIe PHY + +maintainers: + - Jacky Chou + +description: + The ASPEED PCIe PHY provides the physical layer functionality for PCIe + controllers in the SoC. + +properties: + compatible: + items: + - enum: + - aspeed,ast2600-pcie-phy + - aspeed,ast2700-pcie-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: + Fixed 100MHz reference clock provided on the board. + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@1e6ed200 { + compatible = "aspeed,ast2600-pcie-phy"; + reg = <0x1e6ed200 0x100>; + clocks = <&pcie_refclk>; + #phy-cells = <0>; + }; -- 2.34.1