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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3515abb7117sm11761823eec.3.2026.10.07.18.51.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Oct 2026 18:51:05 -0700 (PDT) From: Shawn Guo To: Vinod Koul Cc: Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa , Bartosz Golaszewski , Taniya Das , Krishna Kurapati , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 3/3] phy: phy-snps-eusb2: Enable AHB2PHY bus clock on Nord Date: Thu, 8 Oct 2026 09:50:17 +0800 Message-ID: <20261008015017.3359804-4-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261008015017.3359804-1-shengchao.guo@oss.qualcomm.com> References: <20261008015017.3359804-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: thfRQW5J_lSlgmAXH30ODGS1-JAB5liU X-Authority-Analysis: v=2.4 cv=AbwkjHXG c=1 sm=1 tr=0 ts=6ac6f70b cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=-9G34wqzeZZRMG-dpk0A:9 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA4MDAwNyBTYWx0ZWRfX4BzpFrP10S5D MCcLU/AVtp8Tqq96g51qG0Mq7XPUiZrg0USOG9RTNvj65nNKzTPSVh20VitDw/Z4agHcwz1iVdc NZO4GBHMwmnDjSkUo4TwITUDTq0O1ss= X-Proofpoint-ORIG-GUID: thfRQW5J_lSlgmAXH30ODGS1-JAB5liU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA4MDAwNyBTYWx0ZWRfX+dsE3xtk892f zKeXZCFnVEe0r+dSHPdPRPFjXB9rw4IxhyJiV39CQAgjOkieBchLjlNL+Ot2Z8hXwYHj0pdSBZC IgdPg220FspuzsHUcYj8TA3HW/VkIrhvy8AprQNY/8SvW94StlYaNFHhr9W00VuaVL3ymvT9xFB IzNGL8qLVJL1bZOj7AAdNd0Xo0it4WQU5A8A8/PFXFZvO8QIsUgKFq9T1UxKMlZATwC/fvBg1fc 4VZXgpg1dThTs0zPNKtMnHt1DWz6X66uMvde4ReYX5iFIIwc/v4JokVQJiLpIot/OIAJdZk3zT3 wzus/xKZ5BsqT/D8+2JuK09Z6DODxV0hmdTykXtAK8NHSoTwW71Afkti93TtKg0apbmq5BPGIBB tnmqwV6UugtXyoMQ0acmYnotVArOT4EGujsSVwb72+Pa2EwwDbVwETjSBisromjz84KBuAsUcEj LQ7RSaoGcDL0D2vYH8A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-08_01,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 clxscore=1015 suspectscore=0 priorityscore=1501 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610080007 On Nord, the eUSB2 PHY registers sit behind the AHB2PHY_0 bridge, gated by NE_GCC_AHB2PHY_CLK. The Nord PHY currently matches the sm8550 fallback, which only requests the "ref" clock, so the bridge clock is never enabled by the PHY. When nothing else holds it, e.g. on boards where only the USB20-only controller is in use, clk_disable_unused() gates the bridge and PHY init accesses go nowhere: xhci-hcd xhci-hcd.2.auto: can't setup: -110 Add Nord-specific match data that requests both "ref" and "bus" clocks, reusing the existing Qualcomm init sequence. The bus clock is enabled and disabled together with the ref clock in phy init/exit. Signed-off-by: Shawn Guo --- drivers/phy/phy-snps-eusb2.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2.c index af4fa17ac6cb..8429599f428b 100644 --- a/drivers/phy/phy-snps-eusb2.c +++ b/drivers/phy/phy-snps-eusb2.c @@ -452,6 +452,16 @@ static const struct snps_eusb2_phy_drvdata sm8550_snps_eusb2_phy = { .num_clks = ARRAY_SIZE(qcom_eusb2_hsphy_clock_names), }; +static const char * const nord_eusb2_hsphy_clock_names[] = { + "ref", "bus", +}; + +static const struct snps_eusb2_phy_drvdata nord_snps_eusb2_phy = { + .phy_init = qcom_snps_eusb2_hsphy_init, + .clk_names = nord_eusb2_hsphy_clock_names, + .num_clks = ARRAY_SIZE(nord_eusb2_hsphy_clock_names), +}; + static int snps_eusb2_hsphy_init(struct phy *p) { struct snps_eusb2_hsphy *phy = phy_get_drvdata(p); @@ -608,6 +618,9 @@ static int snps_eusb2_hsphy_probe(struct platform_device *pdev) static const struct of_device_id snps_eusb2_hsphy_of_match_table[] = { { + .compatible = "qcom,nord-snps-eusb2-phy", + .data = &nord_snps_eusb2_phy, + }, { .compatible = "qcom,sm8550-snps-eusb2-phy", .data = &sm8550_snps_eusb2_phy, }, { -- 2.43.0