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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-16166121f2asm14522277c88.4.2026.10.08.01.10.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Oct 2026 01:10:56 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Taniya Das , Jagadeesh Kona , Bryan O'Donoghue , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH v2 1/4] dt-bindings: clock: qcom,sm8450-videocc: Fix clock inputs for Glymur Date: Thu, 8 Oct 2026 16:10:33 +0800 Message-ID: <20261008081036.3492003-2-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261008081036.3492003-1-shengchao.guo@oss.qualcomm.com> References: <20261008081036.3492003-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: tU9NHtXF9fzWtRH1bgbfm1ddinZazHFL X-Authority-Analysis: v=2.4 cv=E4dYNqdl c=1 sm=1 tr=0 ts=6ac75012 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=3WhL5buBUIyFYQ3kjXcA:9 a=Fk4IpSoW4aLDllm1B1p-:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA4MDAzMiBTYWx0ZWRfX+5c7Z0FZUJy5 7VpCYOEo5Aimpj4kgP6Y8kwl0TJYGvEmNUa5Ei/q5t1ZCwTCizi6co7BPzxPHXuz9XrRcFdQ2D/ Ee438b4juDoJA1NX8lqNG8Wa2skeFOQ= X-Proofpoint-GUID: tU9NHtXF9fzWtRH1bgbfm1ddinZazHFL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA4MDAzMiBTYWx0ZWRfX3H2m6DFOYdnQ kLIpCHQjs2aMSS8urWREekV1ht0JdvF6+m6RP4pzcU3q0dpG1M9TM0IzVwIqEcLmLBEOQLk8hH/ 7l8A5AgTstzfvj1It78ran8ySPSXjZBAY+jYvSCSllhJaoqwEfcOsbZxQFHooYtI+klBErndHqu ZiibrR6KioOF8cSBFYbAFfaOmn1udqrwRgT5oszgA/pUqaL++S5oXfMwkL1HsONH3RU1tfENspU 2ZJ9976/ac+OUF38VsBVccwAMO0S8v+VDQ7vyKppU9L06yZGi9Udj7E/Q97pjoxv4Wd4eXy29iB kT2xZxLtAMGEOwQk/CjzxuvGDFbfMMMgMmn+sqEiZbtFC6f55iPTvH7y6ua6fqahChT2tQS6Yqx hgCJNhyC7Uy+IK+mTi10ZHt81GNeGjhIMpd4SGVRtMPn5Muugyr94fhopwPmMRTiAVkayJMnYfM r+vYs/CiIM4AHhyZDlg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-08_03,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 phishscore=0 spamscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610080032 The schema describes exactly two clock inputs for every compatible it covers, a board XO and a video AHB clock from GCC. That does not match the video clock controller found on Glymur, Nord and SM8750. Per the hardware documentation, the controller on these SoCs has three clock inputs: the board XO, the always-on board XO that feeds its PLL reference, and the 32 kHz chip sleep clock that sources its sleep clock generator. It has no AHB clock input. The AHB clock the controller uses for itself is generated inside the block from the XO input. Because the schema stops at two items, the sleep clock input cannot be described in device tree at all, and the second item is described as a clock that is not routed into the controller. Describe three inputs for the Glymur, Nord and SM8750 compatibles and keep the existing two-input description for the remaining compatibles. Assisted-by: LLM Signed-off-by: Shawn Guo --- .../bindings/clock/qcom,sm8450-videocc.yaml | 26 ++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index e985a450451d..9bd746afbc11 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -42,9 +42,8 @@ properties: - qcom,x1p42100-videocc clocks: - items: - - description: Board XO source - - description: Video AHB clock from GCC + minItems: 2 + maxItems: 3 power-domains: description: @@ -79,6 +78,27 @@ allOf: then: required: - required-opps + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-videocc + - qcom,nord-videocc + - qcom,sm8750-videocc + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board always-on XO source + - description: Sleep clock source + else: + properties: + clocks: + items: + - description: Board XO source + - description: Video AHB clock from GCC unevaluatedProperties: false -- 2.43.0