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Miller" , Eric Dumazet , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Heiner Kallweit , Russell King , David Wu , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Coia Prant , Jiawen Wu Subject: [PATCH net-next v11 1/6] net: pcs: xpcs: add ANRESTART support for SGMII link recovery Date: Fri, 9 Oct 2026 01:51:55 +0800 Message-ID: <20261008175225.3375274-2-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261008175225.3375274-1-coiaprant@gmail.com> References: <20261008175225.3375274-1-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On some hardware using the DesignWare XPCS IP (e.g., RK3568 MAC side SGMII), the PCS does not automatically restart auto-negotiation when the link goes down and comes back up. Without an explicit ANRESTART, the link stays down forever. Add BMCR_ANRESTART in two places: 1. In xpcs_config_aneg_c37_sgmii(), when starting AN, set ANRESTART alongside ANENABLE to initiate a fresh negotiation. 2. In xpcs_get_state_c37_sgmii(), when link is down and AN completion is detected, clear the interrupt and trigger ANRESTART to restart the negotiation process. Propagate the return value of the restart so errors are not silently ignored. The restart cannot go through the .pcs_an_restart op: phylink only calls it for 802.3z interfaces, and SGMII is not one. Changing hardware state from pcs_get_state() is already done elsewhere in this driver (xpcs_get_state_c73() calls xpcs_soft_reset() and xpcs_do_config()), so the same pattern is used here. The latch is cleared before issuing the restart, not after: clearing it afterwards would discard a freshly latched ANCMPLT from the new negotiation. If an MDIO access fails at this point, it indicates an unrecoverable hardware condition until reset. Also clear DW_VR_MII_AN_INTR_STS in xpcs_config_aneg_c37_sgmii() before starting AN, matching what xpcs_config_aneg_c37_1000basex() already does. On the non-inband path the function now returns the result of that write instead of the DIG_CTRL1 modify. Update the comment in xpcs_config_aneg_c37_sgmii() to note that although the DesignWare databook says AN restart is not needed for MAC side SGMII, some implementations (e.g. Rockchip RK3568) require it to recover the link after a disconnect. This is not a fix for an existing mainline platform: the affected platform (RK3568 XPCS) is introduced later in the same series. Tested-by: Jiawen Wu Tested-by: Maxime Chevallier Signed-off-by: Coia Prant --- drivers/net/pcs/pcs-xpcs.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index b415b93d77c15..6466e0ff2a98b 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -761,7 +761,9 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, * DW xPCS used with DW EQoS MAC is always MAC side SGMII. * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic * speed/duplex mode change by HW after SGMII AN complete) - * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN) + * 5) VR_MII_AN_INTR_STS = 0x0 (Clear CL37 AN complete status) + * 6) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN) + * VR_MII_MMD_CTRL Bit(9) [AN_RESTART] = 1b (Restart SGMII AN) * * Note that VR_MII_MMD_CTRL is MII_BMCR. * @@ -769,7 +771,14 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from * PHY about the link state change after C28 AN is completed * between PHY and Link Partner. There is also no need to - * trigger AN restart for MAC-side SGMII. + * trigger AN restart for MAC-side SGMII on most devices. + * + * Note: While the DesignWare databook states that AN restart is + * not needed for MAC side SGMII, some implementations (e.g. + * Rockchip RK3568) exhibit a timing quirk when integrated with + * phylink and do not restart AN automatically when the link + * comes back up. An explicit AN restart is required on those + * parts to recover the link after a disconnect. */ mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); if (mdio_ctrl < 0) @@ -816,9 +825,14 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, if (ret < 0) return ret; + /* Clear CL37 AN complete status */ + ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); + if (ret < 0) + return ret; + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, - mdio_ctrl | BMCR_ANENABLE); + mdio_ctrl | BMCR_ANENABLE | BMCR_ANRESTART); return ret; } @@ -1093,9 +1107,18 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs, return 0; } - /* Clear AN complete status or interrupt */ - if (state->an_complete) - xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); + if (state->an_complete) { + /* Clear AN complete status or interrupt */ + ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); + if (ret < 0) + return ret; + + /* Initiate the next round of AN */ + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, BMCR_ANRESTART, + BMCR_ANRESTART); + if (ret < 0) + return ret; + } return 0; } -- 2.47.3