From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 371B34C9DFC; Fri, 9 Oct 2026 10:59:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791543580; cv=none; b=QIrWTCfe5fPivwBw445YUbfM8GGNmakAengroJunfCs5JyBJvNzOqXQ5rj8zZuk/uXjHNoQ+7fCQHvR7c2LlRtJTfNVU4trFX2PIbqNqvoRCgDqClxbgdXPP0gaJQhPlgUohshmg92QUcRRW7KStih5Fx+PhoyScN4Hzs59o5kQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791543580; c=relaxed/simple; bh=6qmV5fP/ovYkMChG07yhC6ChgksYfCJp8P8sxHcAz/c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PrMlX/lTyWT4TKHSDAbaqr5XBylhRVBBS8JKG0V+h31lM1/YXCiDnoMa/s8K1UTLLDsbJalaI8MWxXJ5Vduep9JXSOWwxwQl4cPvYdtYNEplOgdylrliUguawMSLPaDCbGFv9B1ZaXvJmjMZw6CYnRwWUdOIieO6OUAXH5hnozA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HEIxy9+4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HEIxy9+4" Received: by smtp.kernel.org (Postfix) with ESMTPS id C2AD2C2BCF5; Fri, 9 Oct 2026 10:59:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1791543579; bh=6qmV5fP/ovYkMChG07yhC6ChgksYfCJp8P8sxHcAz/c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HEIxy9+4zeNPdq9qs44GB56GQavy/t14rjVo0RwGjA0/XfB2eSXiZWf5MV0JYf5j6 xlFVzFJ2WIDHK3QSmf6vzQw7e2n9xyZYAsfruyM7dctLeHN/7E3fpu4CdojaA8zmLQ QKz7y8wK6bHH+0IZHR0jIB9Rx9ZpAjJoDKtHkrfyUnJRPV27uQursIek7B+YVOjPyy O5E4uafPq4TErBcSoTxsOba9sJ0zpg30BxoggYOzlZWwpvVhUpctkUCCd9xjzRcy94 0DRptuDwXh+SLIGT4ABuZ8EcFWAcBngQWd/TZcO16QqdxleguNaXiMH/IKDTv+7Jk5 V6evEsyZNni8Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2D44CA6019; Fri, 9 Oct 2026 10:59:39 +0000 (UTC) From: Long Zhao via B4 Relay Date: Fri, 09 Oct 2026 18:57:54 +0800 Subject: [PATCH 1/7] dt-bindings: gpio: pl061: add Ambarella CV75 variant Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261009-cv75-gpio-v1-1-5836bd438423@ambarella.com> References: <20261009-cv75-gpio-v1-0-5836bd438423@ambarella.com> In-Reply-To: <20261009-cv75-gpio-v1-0-5836bd438423@ambarella.com> To: Bartosz Golaszewski , linux-gpio@vger.kernel.org Cc: Linus Walleij , Michael Walle , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Krzysztof Kozlowski , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, Long Zhao , Long Zhao , linux-kernel@vger.kernel.org, Conor Dooley X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791543577; l=2127; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=BkO6pO1YpBBieaeL0yXFXs09zVgjmaMwMQO7kuG29w4=; b=KpPiWFmqKcQNCeK2ynO0/hk6+stoqtqO0pM9jQTs9BILta6+GXNvmRnw9mnB/+mmvmztVvk4d iEpglY3BpWCAoyl8c5SajRUA7RHyi0kcmvHQyJupuN8ogar8P6I9w3Z X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao The CV75 GPIO is a modified PL061. The basic registers have the same names and roles (DAT/DIR/IS/IBE/IEV/IE/MIS/IC). Each bank is 32-bit and 32 lines and adds MASK and ENABLE, so it is not register-compatible with the ARM PL061 and arm,pl061 must not be used as a fallback. The AMBA core matches the PL061 driver by PrimeCell ID, not by the DT compatible string. These blocks do not implement the standard PL061 ID (0x00041061) in the ID registers, so arm,primecell-periphid is required and is fixed to 0x000e8061; the driver uses that ID to select the Ambarella layout. gpio-ranges is required because each bank is a slice of the SoC pinctrl pin space. Acked-by: Conor Dooley Signed-off-by: Long Zhao --- .../devicetree/bindings/gpio/pl061-gpio.yaml | 25 +++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml b/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml index 4d970e55104b..c22dd8a1d2c1 100644 --- a/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml @@ -15,7 +15,9 @@ select: properties: compatible: contains: - const: arm,pl061 + enum: + - arm,pl061 + - ambarella,cv75-gpio required: - compatible @@ -25,7 +27,9 @@ properties: compatible: items: - - const: arm,pl061 + - enum: + - ambarella,cv75-gpio + - arm,pl061 - const: arm,primecell reg: @@ -64,6 +68,21 @@ required: - "#gpio-cells" - gpio-controller -additionalProperties: false +allOf: + - $ref: /schemas/arm/primecell.yaml# + - if: + properties: + compatible: + contains: + const: ambarella,cv75-gpio + then: + properties: + arm,primecell-periphid: + const: 0x000e8061 + required: + - arm,primecell-periphid + - gpio-ranges + +unevaluatedProperties: false ... -- 2.34.1