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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-169a442956asm4151609c88.16.2026.10.08.21.50.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Oct 2026 21:50:39 -0700 (PDT) From: Varadarajan Narayanan Date: Fri, 09 Oct 2026 10:20:00 +0530 Subject: [PATCH v6 6/6] phy: qcom: snps-femto-v2: Add IPQ9650 support Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261009-phy-v6-6-50408e45bcc1@oss.qualcomm.com> References: <20261009-phy-v6-0-50408e45bcc1@oss.qualcomm.com> In-Reply-To: <20261009-phy-v6-0-50408e45bcc1@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Manu Gautam , Stephen Boyd , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA5MDAxOSBTYWx0ZWRfX/zwecSzsGOTw lq67DPZieFAb6cPjvBsV5uhk5/KsToZ8Sev2HzzChcg93SCozvWVnuhSJOKLlfSqpd8YIzHzEgg mkt9xb/vXijbDHSSjVBJA910HqKcnkQ= X-Authority-Analysis: v=2.4 cv=MMT1C8Zl c=1 sm=1 tr=0 ts=6ac872a1 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=uK7fivOqSnnNXXB6uWgA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-GUID: cu1DoMlOFhIMk2JsAZDCVJrxeH56069S X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA5MDAxOSBTYWx0ZWRfXx+zBNoZzaY+T M4LMl0CCM9dLm5tdf3lUHWPV77MX0GsHRTzxvSyXxsPpwEwfHxwhPgVglEJGcXQNXgfIgS17UzW tmirGbNpYAPLw+KWZqaEsfVKpGxb3MUrFXWiThghxzebAkPbVxJpBflVKr7e59NrWfL/ru3Dn7d lFJYndoe+UrQN7XZpT/lm8nHnDE05xesOe1PwAg+fTnla7/WEz5ok/O14S1D4hRgFktCSMZnszQ 27Ey9VXdjEX20aSVE1eb0Qtsopq4ndrQdFLD2tyF3xn0LAbdRQLHkzgumJ2VeTVnkROOkEVsN3Z c7JOeasljK0CZdakr7IMA41ZO3Bw3WZBlrUwTHaVJitD+9eRpMUCLcZ40vGBvrEekpsfqg2OHPi RrC/8CIzdiD1Dn+pk/Ie7nWx+tIuOSKxhK50nRwXANRf8BNzhrymycrr14x4IZ9bblHOifjpz4S gWaFlcwdGHqkcGgA/8w== X-Proofpoint-ORIG-GUID: cu1DoMlOFhIMk2JsAZDCVJrxeH56069S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-09_02,2026-10-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 phishscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610090019 Add the 6 nm SNPS femto USB2 PHY configuration needed by IPQ9650. The PHYs on this SoC require a dedicated init sequence and override parameters before they can be enabled. Signed-off-by: Varadarajan Narayanan --- drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 63 +++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c index 2e37b39dabba..0dae8369671a 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -3,6 +3,7 @@ * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -29,12 +30,15 @@ #define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50) #define POR BIT(1) +#define ATERESET BIT(0) #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) #define SIDDQ BIT(2) #define RETENABLEN BIT(3) #define FSEL_MASK GENMASK(6, 4) #define FSEL_DEFAULT (0x3 << 4) +#define FSEL_24MHZ FIELD_PREP_CONST(FSEL_MASK, 2) +#define VATESTENB_MASK GENMASK(1, 0) #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58) #define VBUSVLDEXTSEL0 BIT(4) @@ -57,6 +61,13 @@ #define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3 (0x78) #define PARAM_OVRD_MASK 0xFF +#define USB2_PHY_USB_PHY_HS_PHY_TEST0 0x80 +#define TESTDATAIN_MASK GENMASK(7, 0) + +#define USB2_PHY_USB_PHY_HS_PHY_TEST1 0x84 +#define TESTDATAOUTSEL BIT(4) +#define TESTCLK BIT(6) + #define USB2_PHY_USB_PHY_CFG0 (0x94) #define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0) #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) @@ -78,6 +89,9 @@ #define LS_FS_OUTPUT_IMPEDANCE_MASK GENMASK(3, 0) +#define USB2_PHY_USB_PHY_FSEL_SEL 0xb8 +#define FSEL_SEL BIT(0) + static const char * const qcom_snps_hsphy_vreg_names[] = { "vdda-pll", "vdda33", "vdda18", }; @@ -330,6 +344,17 @@ static const struct override_param ls_fs_output_impedance_sc7280[] = { { 1310, 0 }, }; +static const struct override_param_map ipq9650_snps_6nm_phy[] = { + { + "qcom,pre-emphasis-amplitude-bp", + preemphasis_amplitude_sc7280, + ARRAY_SIZE(preemphasis_amplitude_sc7280), + USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1, + PREEMPHASIS_AMPLITUDE_MASK, + }, + {}, +}; + static const struct override_param_map sc7280_snps_7nm_phy[] = { { "qcom,hs-disconnect-bp", @@ -418,6 +443,32 @@ static const struct phy_reg_config hs_5nm_phy_post_tuning[] = { { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0 }, }; +static const struct phy_reg_config hs_6nm_phy_pre_tuning[] = { + { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, UTMI_PHY_CMN_CTRL_OVERRIDE_EN }, + { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, POR }, + { USB2_PHY_USB_PHY_FSEL_SEL, FSEL_SEL, FSEL_SEL }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, FSEL_MASK, FSEL_24MHZ }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, PLLBTUNE, PLLBTUNE }, + { USB2_PHY_USB_PHY_REFCLK_CTRL, REFCLK_SEL_MASK, REFCLK_SEL_DEFAULT }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, VBUSVLDEXTSEL0, VBUSVLDEXTSEL0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL1, VBUSVLDEXT0, VBUSVLDEXT0 }, +}; + +static const struct phy_reg_config hs_6nm_phy_post_tuning[] = { + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, VREGBYPASS, VREGBYPASS }, + { USB2_PHY_USB_PHY_UTMI_CTRL5, ATERESET, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_TEST1, TESTDATAOUTSEL, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_TEST1, TESTCLK, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, VATESTENB_MASK, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_TEST0, TESTDATAIN_MASK, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N }, + { USB2_PHY_USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM }, + { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 0 }, + { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0 }, +}; + static int qcom_snps_hsphy_init(struct phy *phy) { struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); @@ -512,6 +563,14 @@ static const struct phy_config_data hs_5nm_phy = { .num_post_tuning = ARRAY_SIZE(hs_5nm_phy_post_tuning), }; +static const struct phy_config_data hs_6nm_phy = { + .pre_tuning = hs_6nm_phy_pre_tuning, + .num_pre_tuning = ARRAY_SIZE(hs_6nm_phy_pre_tuning), + .override = ipq9650_snps_6nm_phy, + .post_tuning = hs_6nm_phy_post_tuning, + .num_post_tuning = ARRAY_SIZE(hs_6nm_phy_post_tuning), +}; + static const struct phy_config_data hs_7nm_phy = { .pre_tuning = hs_5nm_phy_pre_tuning, .num_pre_tuning = ARRAY_SIZE(hs_5nm_phy_pre_tuning), @@ -529,6 +588,10 @@ static const struct of_device_id qcom_snps_hsphy_of_match_table[] = { .compatible = "qcom,usb-snps-hs-5nm-phy", .data = &hs_5nm_phy, }, + { + .compatible = "qcom,ipq9650-usb-hs-phy", + .data = &hs_6nm_phy, + }, { .compatible = "qcom,usb-snps-hs-7nm-phy", .data = &hs_7nm_phy, -- 2.34.1