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Fri, 9 Oct 2026 05:19:21 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66CE.mail.protection.outlook.com (10.167.240.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.522.6 via Frontend Transport; Fri, 9 Oct 2026 05:19:21 +0000 Received: from ubuntu (unknown [172.20.64.99]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id C6D0643B1083; Fri, 9 Oct 2026 13:18:46 +0800 (CST) From: Jelly Jia To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.murphy@arm.com Cc: devicetree@vger.kernel.org, Frank.Li@kernel.org, cix-kernel-upstream@cixtech.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jelly.Jia@cixtech.com Subject: [PATCH v2 0/6] dmaengine: arm-dma350: Add slave support and CIX Sky1 integration Date: Fri, 9 Oct 2026 13:18:40 +0800 Message-ID: <20261009051846.1115962-1-Jelly.Jia@cixtech.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260907033404.596839-1-Jelly.Jia@cixtech.com> References: <20260907033404.596839-1-Jelly.Jia@cixtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CE:EE_|TY1PPF4CBD9505D:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: d436d6b6-1e4f-470c-8396-08df25c4e01d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|23010399003|1800799024|36860700016|376014|7416014|6133799003|22082099003|18002099003|10067099003|5023799004|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: X9/Zr3ex8/OwTEAnzbBJB3zlFHo0wFI9BsQmmAKd5y2p7qSqvbsoUD7NyyM3q7ehugWr9iGEf0Y+Og06d676K7nP1BMQaCmDbz03W0TRmvqC13Se4IqadQ5QsbF1VgEFOI06Oyw8Ypp6MgObebUav2GNljix1P+G9BnK8KtnmF8sCTGRQ1TM3q1fk0CXKwQfbrhWFiOKnke7uOw1bFLCoVhflrk20I7bj8JAPwpco43Nvtf/7060v05NoT8g+2kH1QpAehlSB1wmmG+30Iy1gv5KLmjeo3wefhsRSdnMRB20LvoeEHojG8615ReeNLtQjceHPScBSIWgyNzK5n1UyrzLChHbFA2pAzllxg2FtVQaEWFYJ9pXbNsHCqfIRiiL+OFCkcjMQboZRoIbfl0g1Wa0mQxILIbL6dRyYYpoplhpo0HLYYmDwtynDrpMn5ui X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2026 05:19:21.0009 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d436d6b6-1e4f-470c-8396-08df25c4e01d X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CE.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY1PPF4CBD9505D Hello, This series adds slave transfer support to the Arm DMA-350 driver and the CIX Sky1 SoC integration around it. Patch 1 fixes the CH_CTRL_USESRCTRIGIN definition: the source trigger enable bit is bit 25, not bit 26 (which is the destination trigger enable bit). Unchanged since v1. Patch 2 adds slave transfer support to the Arm DMA-350 driver: scatter-gather and cyclic preparation, command-list allocation, per-channel resource mapping and residue reporting. Slave transfers are needed to serve peripheral requests, for example the audio FIFOs of the CIX Sky1 audio subsystem. Patch 3 is new in v2: it syncs the slave command list before starting a transfer. The command list is mapped with dma_map_single(), so without the sync a non-coherent DMA-350 may read stale command words and the transfer stalls after the first command. Patch 4 documents the CIX Sky1 DMA-350 integration in the arm,dma-350 binding: the Sky1 controller keeps the generic compatible and adds a "cix,sky1-dma350" device compatible, with clocks, resets, interrupt routing through a syscon phandle and an optional reserved memory pool described on the controller node. Patch 5 adds the matching driver support, which manages those resources; slave resources are mapped with dma_map_resource() and translated by the DMA API through the parent bus dma-ranges. Patch 6 adds the two Sky1 instances (FCH and AUDSS) to the SoC devicetree, each under a simple-bus node describing the bus integration. Changes since v1: - The wrapper node is gone. The Sky1 DMA-350 is described by a single device node with "cix,sky1-dma350", "arm,dma-350" and its real MMIO region, carrying the clock, reset and interrupt routing that v1 kept on the wrapper; the separate cix,sky1-dma350 binding and the wrapper driver are dropped. The integration and the block are one device, and the MMIO is unchanged. Thanks to Krzysztof Kozlowski and Conor Dooley for the review. - The FCH and AUDSS DMA-350 masters sit behind SoC interconnect windows in a static DMA address domain, so their DMA view differs from the CPU physical view; the windows are fixed before Linux boots, so Linux cannot manage them as an interconnect. They are described with a generic "simple-bus" address-domain parent carrying the window "dma-ranges", not with a CIX DMA wrapper device: the parent has no device-specific or vendor wrapper compatible, only the generic "simple-bus" compatible, and no reg, clocks, resets or driver of its own. The OF DMA core builds dev->dma_range_map from that parent property and the DMA API applies it; the driver has no private translation. Same shape as the mainline Agilex5 and Marvell AC5 buses; patch 6 explains the hardware in detail. - Patch 2 now allocates the command list with kmalloc()/dma_map_single() instead of dma_alloc_coherent(), because it is freed from the virt-dma tasklet where dma_free_coherent() may not be called; it picks a free trigger-capable channel in .of_xlate(); and it reads the link address registers in a retry loop, since the channel can step the link pointer between the two reads. - Patch 3 is new, see above. - Patch 5 merged the Sky1 integration into arm-dma350.c; slave resources are mapped with dma_map_resource() and translated by the DMA API through the parent bus dma-ranges. The series is based on v7.3-rc1. Testing: - Built for arm64 with GCC 12.3, no new warnings; sparse clean; checkpatch --strict clean. - dt_binding_check and dtbs_check pass for the new binding and nodes. - Runtime-tested on a CIX Sky1 (Radxa Orion O6) board: both the FCH and the AUDSS DMA-350 instances probe and transfer data, and audio playback through the AUDSS DMA-350 runs without underruns. Assisted-by: LLM checkpatch sparse dt_binding_check dtbs_check Signed-off-by: Jelly Jia Jelly Jia (6): dmaengine: arm-dma350: Fix source trigger bit dmaengine: arm-dma350: Add slave and cyclic transfer support dmaengine: arm-dma350: Sync the slave command list before starting dt-bindings: dma: arm,dma-350: Document the CIX Sky1 integration dmaengine: arm-dma350: Add CIX Sky1 integration support arm64: dts: cix: Describe the Sky1 DMA-350 bus integration .../devicetree/bindings/dma/arm,dma-350.yaml | 33 +- arch/arm64/boot/dts/cix/sky1.dtsi | 66 +- drivers/dma/Kconfig | 4 + drivers/dma/arm-dma350.c | 717 +++++++++++++++++- 4 files changed, 783 insertions(+), 37 deletions(-) base-commit: cee9395acd8043be0644b25c34bfa86623f2b935 -- 2.54.0