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Fri, 9 Oct 2026 05:19:23 +0000 X-MS-Exchange-Authentication-Results: mx.microsoft.com 1; spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG1PEPF000082E3.mail.protection.outlook.com (10.167.240.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.522.6 via Frontend Transport; Fri, 9 Oct 2026 05:19:22 +0000 Received: from ubuntu (unknown [172.20.64.99]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 611A843B1089; Fri, 9 Oct 2026 13:18:49 +0800 (CST) From: Jelly Jia To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.murphy@arm.com Cc: devicetree@vger.kernel.org, Frank.Li@kernel.org, cix-kernel-upstream@cixtech.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jelly.Jia@cixtech.com Subject: [PATCH v2 6/6] arm64: dts: cix: Describe the Sky1 DMA-350 bus integration Date: Fri, 9 Oct 2026 13:18:46 +0800 Message-ID: <20261009051846.1115962-7-Jelly.Jia@cixtech.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261009051846.1115962-1-Jelly.Jia@cixtech.com> References: <20260907033404.596839-1-Jelly.Jia@cixtech.com> <20261009051846.1115962-1-Jelly.Jia@cixtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E3:EE_|TY0PR06MB5753:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 0b255bc8-6ced-4330-6de5-08df25c4e124 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|23010399003|36860700016|82310400026|1800799024|376014|6133799003|22082099003|56012099006|5023799004|18002099003|10067099003|4143699003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1La8+Pj7KjybT9YelGcxbRfOZfmbRhgqqjlVIo9giSECg3+RTBW42P1kP5+krv74jPvN7wrSBAzhJ6B5ab17O6xy1Xs+fs8dBJQntwndz3/vn+nrZxOcYArbWnbcibau9Xb5xDwqped1O/+FRYoKRqfH8FYLz0QPB4KfTMZhI5RgyJtvygcEBJ0eX2FA1hZGiwroGl88CdukEjgkmM8PK3T6iw4eRitx7jt8F3soeQgdfUxqr0o1CejpzobV/BnEKcSao0MrMNxPN8d3pYx40mk2TaXVUZhhdmv2fkxg2tsz2ZfGs9l0lpbb2Sr77ci3wVxo4do64q3Dt6XrD6ZrjMkXhCor/aOqc5sHUNx9H/2oi8uyKBUXga4eCqqgAV8pu132Ta8s1d32DVsg/IuDBj0J7NYNdjM3B6yUo7yftQOzC/QYZxBpZTeLmILOYMRI X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2026 05:19:22.6060 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0b255bc8-6ced-4330-6de5-08df25c4e124 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E3.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY0PR06MB5753 The FCH DMA-350 controller sits behind an interconnect window, so the addresses its DMA master uses differ from the CPU physical addresses. Describe the integration as a bus node carrying the dma-ranges of that window, with the controller itself as a child, and give the controller the SoC compatible and the clock feeding it. The AUDSS DMA-350 controller is described the same way, with its clock, reset and the AUDSS CRU syscon that gates the channel interrupts before they reach the AP interrupt controller. It has no consumer in the SoC dtsi yet: the audio controllers that use it are not described upstream. Assisted-by: LLM checkpatch sparse dt_binding_check dtbs_check Signed-off-by: Jelly Jia --- v1 -> v2: - The DMA-350 nodes are no longer wrappers with the generic controller as a child: each Sky1 DMA-350 is a single device node with the "cix,sky1-dma350", "arm,dma-350" compatible, its real MMIO region and the integration resources (clock, reset, interrupt router) that v1 kept on the wrapper. The integration and the block are one device, and the MMIO is the same as the generic node it replaces. - The FCH and AUDSS DMA-350 masters sit behind SoC interconnect windows in a static DMA address domain: the AUDSS masters see the audio register and FIFO block at 0x20000000 and the DRAM window at 0x30000000, which the CPU sees at 0x07010000 and 0xc0000000, and the FCH masters see the 0x040b0000 window at 0x040a0000. Their DMA view of the address space is not the CPU physical view. - The windows are static hardware configuration, set up before Linux starts by the boot firmware / secure world: they are not programmable from Linux and must not be reconfigured by it. There is nothing for a Linux interconnect provider to manage here, so the translation cannot be modeled as one; it is a fixed property of the bus. - It is described the standard devicetree way instead: a generic "simple-bus" parent with an identity "ranges;" and the "dma-ranges" of the window. This is not the rejected v1 wrapper and not a separate DMA wrapper/integration device: the parent has no device-specific or vendor wrapper compatible, only the generic "simple-bus" compatible, no reg, no clocks, no resets, no driver and no private address translation. Its only job is to carry the static translation, so it is only a generic bus/address-domain node. - The "dma-ranges" have to sit on that parent for the OF core to build dev->dma_range_map: of_dma_configure_id() starts the lookup at the device's parent (bus_np = __of_get_dma_parent(np) in drivers/of/device.c), so a "dma-ranges" on the controller node itself would be ignored. The translation is applied by the DMA API, not by driver code: the driver maps slave resources with dma_map_resource() and contains no address parser. - The same shape is used in mainline: the Agilex5 DMA bus (dma-bus@10db0000, a simple-bus with dma-ranges whose controller carries "altr,agilex5-axi-dma", "snps,axi-dma-1.01a") and the Marvell AC5 buses (bus@80500000 with "ranges;" and "dma-ranges", and behind-32bit-controller@7f000000, whose only purpose is the DMA mapping of the devices below it). arch/arm64/boot/dts/cix/sky1.dtsi | 66 +++++++++++++++++++++++++------ 1 file changed, 54 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index 0a820f45feb9..e3bd6c0e383f 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -518,18 +518,29 @@ iomuxc: pinctrl@4170000 { reg = <0x0 0x04170000 0x0 0x1000>; }; - fch_dmac: dma-controller@4190000 { - compatible = "arm,dma-350"; - reg = <0x0 0x4190000 0x0 0x10000>; - interrupts = , - , - , - , - , - , - , - ; - #dma-cells = <1>; + bus@4190000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges = <0x0 0x040a0000 0x0 0x040b0000 0x0 0x00040000>, + <0x0 0x80000000 0x0 0x80000000 0x8 0x00000000>, + <0x80 0x00000000 0x80 0x00000000 0x80 0x00000000>; + + fch_dmac: dma-controller@4190000 { + compatible = "cix,sky1-dma350", "arm,dma-350"; + reg = <0x0 0x04190000 0x0 0x10000>; + clocks = <&scmi_clk CLK_TREE_FCH_DMA_ACLK>; + interrupts = , + , + , + , + , + , + , + ; + #dma-cells = <1>; + }; }; mbox_ap2se: mailbox@5060000 { @@ -576,6 +587,37 @@ mbox_pm2ap: mailbox@65a0080 { cix,mbox-dir = "rx"; }; + bus@7010000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges = <0x0 0x20000000 0x0 0x07010000 0x0 0x00100000>, + <0x0 0x30000000 0x0 0xc0000000 0x0 0x20000000>; + + audss_dmac: dma-controller@7010000 { + compatible = "cix,sky1-dma350", "arm,dma-350"; + reg = <0x0 0x07010000 0x0 0x10000>; + clocks = <&audss_cru CLK_DMAC_AXI>; + resets = <&audss_cru AUDSS_DMAC_SW_RST>; + /* + * The AUDSS CRU gates each DMAC channel interrupt + * before it reaches the GIC. AUDSS_DMAC_INFO_AP_IRQ + * is at CRU offset 0x54. + */ + cix,irq-router = <&audss_cru>; + interrupts = , + , + , + , + , + , + , + ; + #dma-cells = <1>; + }; + }; + audss_cru: clock-controller@7110000 { compatible = "cix,sky1-audss-cru"; reg = <0x0 0x07110000 0x0 0x10000>; -- 2.54.0