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[213.45.9.252]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4a18be96549sm55116365e9.6.2026.10.09.00.33.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Oct 2026 00:33:39 -0700 (PDT) From: Christian Marangi To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Christian Marangi , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] PM / devfreq: add Airoha SoC Subsystem devfreq driver Date: Fri, 9 Oct 2026 09:33:29 +0200 Message-ID: <20261009073330.18175-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261009073330.18175-1-ansuelsmth@gmail.com> References: <20261009073330.18175-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add simple Airoha SoC devfreq driver. This simple driver register a driver from a given clock and register a passive governor to scale the frequency with the CPU frequency. Each subsystem is scaled to idle, nominal or turbo state based on the CPU frequency to reflect the performance state required by the SoC. required-opp on the CPU frequency will be used to correctly bind the clock to the related CPU frequency. GSW, NPU, SOE, BUS and many other clock will register this devfreq driver to scale all these internal peripheral from idle to performance mode. Signed-off-by: Christian Marangi --- drivers/devfreq/Kconfig | 10 +++ drivers/devfreq/Makefile | 1 + drivers/devfreq/airoha-subsystem-devfreq.c | 100 +++++++++++++++++++++ 3 files changed, 111 insertions(+) create mode 100644 drivers/devfreq/airoha-subsystem-devfreq.c diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index c999c4a1e567..e8ea0c0af319 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -75,6 +75,16 @@ config DEVFREQ_GOV_PASSIVE comment "DEVFREQ Drivers" +config ARM_AIROHA_SUBSYSTEM_DEVFREQ + tristate "Scaling support for Airoha SoC Subsystems" + depends on ARCH_AIROHA || COMPILE_TEST + select DEVFREQ_GOV_PASSIVE + help + This adds the DEVFREQ driver for the Airoha SoC Subsystems. + + The driver register with the cpufreq notifier and find the right frequency + based on the required OPP set in DT. + config ARM_EXYNOS_BUS_DEVFREQ tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver" depends on ARCH_EXYNOS || COMPILE_TEST diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 404179d79a9d..31cdfe8fb704 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o # DEVFREQ Drivers +obj-$(CONFIG_ARM_AIROHA_SUBSYSTEM_DEVFREQ) += airoha-subsystem-devfreq.o obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o obj-$(CONFIG_ARM_HISI_UNCORE_DEVFREQ) += hisi_uncore_freq.o obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o diff --git a/drivers/devfreq/airoha-subsystem-devfreq.c b/drivers/devfreq/airoha-subsystem-devfreq.c new file mode 100644 index 000000000000..4b89121f7b8e --- /dev/null +++ b/drivers/devfreq/airoha-subsystem-devfreq.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct airoha_devfreq_data { + struct clk *clk; + + struct devfreq_passive_data gov_data; +}; + +static int airoha_devfreq_get_cur_freq(struct device *dev, unsigned long *freq) +{ + struct airoha_devfreq_data *data = dev_get_drvdata(dev); + + *freq = clk_get_rate(data->clk); + + return 0; +} + +static int airoha_devfreq_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct airoha_devfreq_data *data = dev_get_drvdata(dev); + + return clk_set_rate(data->clk, *freq); +} + +static int airoha_devfreq_get_dev_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct airoha_devfreq_data *data = dev_get_drvdata(dev); + + stat->busy_time = 0; + stat->total_time = 0; + stat->current_frequency = clk_get_rate(data->clk); + + return 0; +} + +static struct devfreq_dev_profile airoha_devfreq_devfreq_profile = { + .target = airoha_devfreq_target, + .get_dev_status = airoha_devfreq_get_dev_status, + .get_cur_freq = airoha_devfreq_get_cur_freq +}; + +static int airoha_devfreq_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct airoha_devfreq_data *data; + struct devfreq *devfreq; + int ret; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(data->clk)) + return dev_err_probe(dev, PTR_ERR(data->clk), "failed to get clk\n"); + + ret = devm_pm_opp_of_add_table(dev); + if (ret) + return dev_err_probe(dev, ret, "failed to parse fab freq thresholds\n"); + + dev_set_drvdata(dev, data); + + data->gov_data.parent_type = CPUFREQ_PARENT_DEV; + devfreq = devm_devfreq_add_device(dev, &airoha_devfreq_devfreq_profile, + DEVFREQ_GOV_PASSIVE, &data->gov_data); + + return PTR_ERR_OR_ZERO(devfreq); +} + +static const struct of_device_id airoha_devfreq_match_table[] = { + { .compatible = "airoha,devfreq" }, + {} +}; +MODULE_DEVICE_TABLE(of, airoha_devfreq_match_table); + +static struct platform_driver airoha_devfreq_driver = { + .probe = airoha_devfreq_probe, + .driver = { + .name = "airoha-subsystem-devfreq", + .of_match_table = airoha_devfreq_match_table, + }, +}; +module_platform_driver(airoha_devfreq_driver); + +MODULE_DESCRIPTION("Airoha Devfreq driver"); +MODULE_AUTHOR("Christian Marangi "); +MODULE_LICENSE("GPL"); -- 2.55.0