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Fri, 9 Oct 2026 11:43:45 +0000 (GMT) From: Raghav Sharma To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, peter.griffin@linaro.org, alim.akhtar@samsung.com, sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, conor+dt@kernel.org, raghav.s@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, is.gandhi@samsung.com, ts.amit@samsung.com, pokala.reddy@samsung.com Subject: [PATCH v2 06/14] clk: samsung: clk-pll: Add support for pll_4313 Date: Fri, 9 Oct 2026 17:31:29 +0530 Message-Id: <20261009120137.2801911-7-raghav.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261009120137.2801911-1-raghav.s@samsung.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CMS-MailID: 20261009114348epcas5p209346244d44e4578aa27c061b5fdebd7 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-543,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20261009114348epcas5p209346244d44e4578aa27c061b5fdebd7 References: <20261009120137.2801911-1-raghav.s@samsung.com> From: Alim Akhtar PLLs 4313 are found in the Exynos8855 SoC and it is similar to pll_531x except for CON8 offset, so re-using code for pll_4313 Signed-off-by: Alim Akhtar Signed-off-by: Raghav Sharma --- drivers/clk/samsung/clk-pll.c | 11 ++++++++++- drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 3d837bd74355..7b0756127306 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1306,7 +1306,15 @@ static unsigned long samsung_pll531x_recalc_rate(struct clk_hw *hw, u64 mdiv, fout = parent_rate; pll_con0 = readl_relaxed(pll->con_reg); - pll_con8 = readl_relaxed(pll->con_reg + 20); + if (pll->type == pll_4313) { + /* Offset for PLL_CON8 which hold FDIV different for PLL_4313 + * which is PLL_LOCKTIME_OFFSET - 0x4 + */ + pll_con8 = readl_relaxed(pll->lock_reg - 4); + } else { + pll_con8 = readl_relaxed(pll->con_reg + 20); + } + mdiv = (pll_con0 >> PLL531X_MDIV_SHIFT) & PLL531X_MDIV_MASK; pdiv = (pll_con0 >> PLL531X_PDIV_SHIFT) & PLL531X_PDIV_MASK; sdiv = (pll_con0 >> PLL531X_SDIV_SHIFT) & PLL531X_SDIV_MASK; @@ -1729,6 +1737,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_309: case pll_531x: case pll_4311: + case pll_4313: init.ops = &samsung_pll531x_clk_ops; break; case pll_1031x: diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 2457cf47c109..4825e1f5b9db 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -49,6 +49,7 @@ enum samsung_pll_type { pll_0718x, pll_0732x, pll_4311, + pll_4313, pll_1017x, pll_1031x, pll_a9fracm, -- 2.34.1