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linux-arm-kernel@lists.infradead.org, Stefan Wahren , Martin Lukas , Michael Heimpold Subject: [PATCH V6 2/2] arm64: dts: freescale: Add chargebyte Charge Control Y Date: Fri, 9 Oct 2026 20:15:51 +0200 Message-ID: <20261009181551.6478-3-wahrenst@gmx.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261009181551.6478-1-wahrenst@gmx.net> References: <20261009181551.6478-1-wahrenst@gmx.net> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:bQobZd8VSnMmTh9sVRJJKiY7GFK2gp1ltlPjykRWFVoSdt/O9/F OXYHChDb36BuV0W5Gh517xuLmgnoVOczGgivDT0quieUowH/VbIlz8goJFt0btvjnjliLAs ZTbmJWY7z0ETeDalfjELZihfjVC6o8t1IzMpPDaFlfcd/80PswxG5y2sUWXHCzH8LbpuYI7 jmHdus8fVdx3a9Ekv4FWw== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:wMmgpVF1sZI=;6Yn4IOD6/H+7gZKeM0bEWUT7x7O 3EBS54xKrX1EOYoDFHMzhnjpmGfUjqPHCgbf5Ck9Vd8hr5NXN3fCUqcSwS9c3lV3zyBRSJcIc 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aJuXV1ouEHVcgS+p/K5oze29v/Ip12SvgwGMMuYS7OhqpB85Ih9XcZAYjqi8KFLSOaPj4oHvI Rjs5IGH43Zc= This adds the support for chargebyte Charge Control Y, which is an Electrical Vehicle Supply Equipment (EVSE) for MCS (Megawatt Charging System) charging stations (according to IEC 61851-23-1). chargebyte Charge Control Y uses phyCORE-i.MX 93 ARM - NXP i.MX93 1.7 GHz - 1 GB DDR4 RAM - up to 8 GB eMMC - 2x 100 MBit/s Ethernet interfaces - 10BASE-T1S Ethernet for MCS communication - CAN interface - separate safety chip - TPM chip - power buffered RTC Co-developed-by: Martin Lukas Signed-off-by: Martin Lukas Co-developed-by: Michael Heimpold Signed-off-by: Michael Heimpold Signed-off-by: Stefan Wahren =2D-- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx93-charge-control-y.dts | 438 ++++++++++++++++++ .../boot/dts/freescale/imx93-phycore-som.dtsi | 2 +- 3 files changed, 440 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/freescale/imx93-charge-control-y.d= ts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/= freescale/Makefile index a80cccf34eb5..5984d3742ef8 100644 =2D-- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -898,6 +898,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx93-11x11-frdm-pixpaper.= dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-14x14-evk.dtb imx93-14x14-evk-mqs-dtbs +=3D imx93-14x14-evk.dtb imx9-mqs.dtbo dtb-$(CONFIG_ARCH_MXC) +=3D imx93-14x14-evk-mqs.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx93-charge-control-y.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-kontron-bl-osm-s.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-lino-verdin-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-lino-verdin-dev.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-charge-control-y.dts b/ar= ch/arm64/boot/dts/freescale/imx93-charge-control-y.dts new file mode 100644 index 000000000000..7c5666cd4730 =2D-- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-charge-control-y.dts @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025-2026 chargebyte GmbH + */ + +/dts-v1/; + +#include +#include "imx93-phycore-som.dtsi" + +/ { + model =3D "chargebyte Charge Control Y"; + compatible =3D "chargebyte,imx93-charge-control-y", "phytec,imx93-phycor= e-som", "fsl,imx93"; + + aliases { + ethernet0 =3D &fec; + ethernet1 =3D &lan8651; + ethernet2 =3D &eqos; + gpio0 =3D &gpio1; + gpio1 =3D &gpio2; + gpio2 =3D &gpio3; + gpio3 =3D &gpio4; + mmc0 =3D &usdhc1; + mmc1 =3D &usdhc2; + rtc0 =3D &rv3028; + rtc1 =3D &bbnsm_rtc; + serial0 =3D &lpuart1; + serial1 =3D &lpuart2; + serial2 =3D &lpuart3; + serial3 =3D &lpuart4; + serial4 =3D &lpuart5; + }; + + chosen { + stdout-path =3D &lpuart1; + }; + + // Heartbeat LED of phyCore is not populated + /delete-node/ leds; + + flexcan1_tc: can-phy0 { + compatible =3D "microchip,mcp2542", "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <1000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "VCC_SD"; + }; + + user_leds: user-leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_user_leds>; + + led_user_green: led-user-green { + color =3D ; + function =3D LED_FUNCTION_BOOT; + gpios =3D <&gpio2 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "timer"; + }; + + led_user_red: led-user-red { + color =3D ; + function =3D LED_FUNCTION_SD; + gpios =3D <&gpio2 25 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "mmc1"; + }; + }; +}; + +// Heartbeat LED of phyCore is not populated +/delete-node/ &pinctrl_leds; + +&eeprom0 { + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + /* Wired ethernet interface */ + eth1_mac_address: base-mac-address@100 { + compatible =3D "mac-base"; + reg =3D <0x100 0x6>; + #nvmem-cell-cells =3D <1>; + }; + + /* MCS ethernet interface */ + eth2_mac_address: base-mac-address@108 { + compatible =3D "mac-base"; + reg =3D <0x108 0x6>; + #nvmem-cell-cells =3D <1>; + }; + }; +}; + +/* Ethernet 2 */ +&eqos { + phy-mode =3D "rmii"; + phy-handle =3D <ðphy2>; + assigned-clocks =3D <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>; + assigned-clock-parents =3D <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates =3D <100000000>, <50000000>; + + nvmem-cells =3D <ð1_mac_address 0>; + nvmem-cell-names =3D "mac-address"; + + status =3D "okay"; +}; + +/* Ethernet 1 */ +&fec { + /* Since MDIO bus is handled by FEC, all PHY strap pins and + * reference clock must be initialized at the same time. + */ + pinctrl-0 =3D <&pinctrl_fec &pinctrl_eqos &pinctrl_eqos_strap>; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + phys =3D <&flexcan1_tc>; + status =3D "okay"; +}; + +&gpio1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio1>, <&pinctrl_lan8651_rst>; + gpio-line-names =3D "", "", "", "X_nRST_LAN", "", + "", "LPUART2_RX", "LPUART2_TX", "CAN1_TX", "CAN1_RX", + "", "SPI_TPM_nCS0", "", "", "", + ""; +}; + +&gpio2 { + gpio-line-names =3D "", "", "", "", "", + "", "", "X_LAN_nIRQ", "X_LAN_nCS", "", + "", "", "", "", "", + "", "", "", "", "", + "", "", "", "", "GREEN_LED", + "RED_LED", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names =3D "SD2_nCD", "", "", "", "", + "", "", "SD2_nRESET", "", "", + "", "", "", "", "", + "", "", "", "", "", + "SOM_EMMC_nRESET", "", "", "", "", + "", "", "", "", "", + "", ""; +}; + +&gpio4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio4>; + gpio-line-names =3D "", "", "X_RTC_nINT", "", "", + "", "", "", "", "", + "", "", "SAFETY_BOOTMODE_SET", "ENET1_RST", "", + "", "", "", "", "", + "", "SOM_EEPROM_WP", "", "SOM_PHY_RESET", "", + "", "", "PMIC_IRQ_B", "nSAFETY_RESET_INT", "SPI_TPM_nINT0"; +}; + +&lpi2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_lpi2c1>; + pinctrl-1 =3D <&pinctrl_lpi2c1_gpio>; + scl-gpios =3D <&gpio1 00 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio1 01 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + rv3028: rtc@52 { + compatible =3D "microcrystal,rv3028"; + interrupts =3D <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio4>; + wakeup-source; + trickle-resistor-ohms =3D <3000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_rtc>; + reg =3D <0x52>; + }; +}; + +&lpspi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpspi1>; + num-cs =3D <1>; + cs-gpios =3D <&gpio1 11 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + tpm@0 { + compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; + reg =3D <0>; + spi-max-frequency =3D <10000000>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <29 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +/* MCS Ethernet SPI */ +&lpspi3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpspi3>; + num-cs =3D <1>; + cs-gpios =3D <&gpio2 8 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + lan8651: ethernet@0 { + compatible =3D "microchip,lan8651", "microchip,lan8650"; + reg =3D <0>; + interrupt-parent =3D <&gpio2>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency =3D <25000000>; + + nvmem-cells =3D <ð2_mac_address 0>; + nvmem-cell-names =3D "mac-address"; + + /* + * Since GPIO reset management for the LAN8651 has not yet been + * implemented, X_nRST_LAN should be retained as a GPIO in + * userspace for the rare case that a reset via SPI does not work. + */ + }; +}; + +&lpuart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&lpuart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart3>; + status =3D "okay"; +}; + +/* Ethernet 2 PHY */ +&mdio { + ethphy2: ethernet-phy@2 { + reg =3D <2>; + compatible =3D "ethernet-phy-id2000.a140"; + clocks =3D <&clk IMX93_CLK_ENET_REF_PHY>; + reset-gpios =3D <&gpio4 13 GPIO_ACTIVE_HIGH>; + reset-assert-us =3D <30>; + reset-deassert-us =3D <50000>; + }; +}; + +/* SD */ +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + cd-gpios =3D <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + bus-width =3D <4>; + disable-wp; + no-sdio; + no-mmc; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins =3D < + MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000057e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x50e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x50e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e + >; + }; + + pinctrl_eqos_strap: eqosstrapgrp { + fsl,pins =3D < + MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x17e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x17e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x17e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x17e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D < + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + MX93_PAD_PDM_CLK__CAN1_TX 0x1382 + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins =3D < + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x382 + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins =3D < + MX93_PAD_ENET1_TXC__GPIO4_IO07 0x382 + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x39e + MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x39e + MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e + >; + }; + + /* X_nRST_LAN is wired to a pull resistor, so it's not floating */ + pinctrl_lan8651_rst: lan8651rstgrp { + fsl,pins =3D < + MX93_PAD_I2C2_SDA__GPIO1_IO03 0x31e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins =3D < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b86 + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b86 + >; + }; + + pinctrl_lpi2c1_gpio: lpi2c1gpiogrp { + fsl,pins =3D < + MX93_PAD_I2C1_SCL__GPIO1_IO00 0x40000b9e + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x40000b9e + >; + }; + + pinctrl_lpspi1: lpspi1grp { + fsl,pins =3D < + MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x186 + MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x186 + MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x186 + MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x186 + MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x186 + >; + }; + + /* PinCtrl MCS LAN SPI */ + pinctrl_lpspi3: lpspi3grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO07__GPIO2_IO07 0x186 + MX93_PAD_GPIO_IO08__GPIO2_IO08 0x186 + MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x186 + MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x186 + MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x186 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins =3D < + MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x30e + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO15__LPUART3_RX 0x31e + MX93_PAD_GPIO_IO14__LPUART3_TX 0x30e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins =3D < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins =3D < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_default: usdhc2grp { + fsl,pins =3D < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x118e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_user_leds: userledgrp { + fsl,pins =3D < + MX93_PAD_GPIO_IO24__GPIO2_IO24 0x31e + MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/a= rm64/boot/dts/freescale/imx93-phycore-som.dtsi index 325e465d0056..489ed3f7fb61 100644 =2D-- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -201,7 +201,7 @@ ldo5: LDO5 { }; =20 /* EEPROM */ - eeprom@50 { + eeprom0: eeprom@50 { compatible =3D "atmel,24c32"; reg =3D <0x50>; pagesize =3D <32>; =2D-=20 2.43.0