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From: Oleg Zadorozhnyi =0A= =0A= The device has an internal net by which one PLL can drive the others: the= =0A= source PLL puts its output on it, and any other PLL can select it as a=0A= reference instead of an external input. The two ends are nothing alike --= =0A= one is driven, the other is selected -- so they are two pins rather than=0A= one: an output pin on the source and an input pin on each destination.=0A= =0A= That keeps each pin honest about what its state means. The source pin=0A= reports whether this PLL is the one driving the net, and setting it takes= =0A= the net over or gives it up; a destination pin reports whether its PLL has= =0A= selected the net, and behaves like any other selectable input. A single=0A= pin would have had to answer both questions at once and could only have=0A= been right about one of them.=0A= =0A= A destination pin whose net no PLL drives reports no signal, as an=0A= external input that lost its clock does. The driver takes the net as=0A= driven when it enabled the source itself or found that configuration=0A= already in place. The net has no signal monitor, and a loaded profile=0A= can drive it with a configuration of its own, so a PLL the device feeds=0A= from the net and holds locked also counts as the net carrying a signal.=0A= A source that failed to take the net over, or whose configuration the=0A= scan found only partly in place, is recorded as a partial owner, so a=0A= retry re-runs the enable instead of being refused as busy; giving the=0A= net up restores the global enable only while the net is still=0A= configured, and the restore is latched as every other write to that=0A= register is. A failed request that moved the owner is announced.=0A= Ownership and the output mutes are read back from the part on resume.=0A= =0A= Signed-off-by: Oleg Zadorozhnyi =0A= Assisted-by: LLM=0A= Signed-off-by: Ali Rouhi =0A= ---=0A= drivers/dpll/sit9531x/core.c | 414 ++++++++++++++++++++++++++++++++++-=0A= drivers/dpll/sit9531x/core.h | 7 +=0A= drivers/dpll/sit9531x/dpll.c | 409 +++++++++++++++++++++++++++++++++-=0A= drivers/dpll/sit9531x/regs.h | 3 +=0A= 4 files changed, 823 insertions(+), 10 deletions(-)=0A= =0A= diff --git a/drivers/dpll/sit9531x/core.c b/drivers/dpll/sit9531x/core.c=0A= index fbac70787ada..c2d6fbd0363f 100644=0A= --- a/drivers/dpll/sit9531x/core.c=0A= +++ b/drivers/dpll/sit9531x/core.c=0A= @@ -3027,6 +3027,381 @@ int sit9531x_clear_notifications(struct sit9531x_de= v *sitdev)=0A= return 0;=0A= }=0A= =0A= +/*=0A= + * Close the debug window on a PLL's EXT page. The key register opens=0A= + * every debug register on that page while it holds the unlock value.=0A= + */=0A= +static int sit9531x_intsync_debug_lock(struct sit9531x_dev *sitdev, u8 ext= _page)=0A= +{=0A= + return sit9531x_write_u8(sitdev,=0A= + SIT9531X_REG(ext_page, SIT9531X_PLL_REG_DEBUG),=0A= + SIT9531X_PLL_DEBUG_LOCK);=0A= +}=0A= +=0A= +/*=0A= + * INTSYNC configuration register values.=0A= + * These are written to the source PLL's EXT page to enable/disable=0A= + * inter-PLL synchronization (lock frequency PLL to phase PLL).=0A= + */=0A= +struct sit9531x_intsync_reg {=0A= + u8 offset;=0A= + u8 en_val;=0A= + u8 dis_val;=0A= +};=0A= +=0A= +static const struct sit9531x_intsync_reg intsync_config[] =3D {=0A= + { 0x2D, 0x02, 0x00 },=0A= + { 0x50, 0x08, 0x00 },=0A= + { 0x51, 0x04, 0x00 },=0A= + { 0x54, 0x02, 0x00 },=0A= + { 0x55, 0x28, 0x20 },=0A= + { 0x5C, 0x0F, 0x00 },=0A= + { 0x5D, 0xFF, 0x00 },=0A= + { 0x6C, 0xDD, 0x00 },=0A= +};=0A= +=0A= +int sit9531x_intsync_src_detect(struct sit9531x_dev *sitdev)=0A= +{=0A= + s8 src =3D -1, partial =3D -1;=0A= + u8 global;=0A= + u8 pll, ext_page;=0A= + int rc, ret, n_en, n_dis;=0A= + unsigned int i;=0A= +=0A= + lockdep_assert_held(&sitdev->multiop_lock);=0A= +=0A= + rc =3D sit9531x_read_u8(sitdev, SIT9531X_REG_INTSYNC_GLOBAL, &global);=0A= + if (rc)=0A= + return rc;=0A= +=0A= + if (!(global & BIT(SIT9531X_INTSYNC_EN_BIT))) {=0A= + sitdev->intsync_src =3D -1;=0A= + sitdev->intsync_partial =3D false;=0A= + return 0;=0A= + }=0A= +=0A= + for (pll =3D 0; pll < SIT9531X_NUM_PLLS; pll++) {=0A= + ext_page =3D SIT9531X_PLL_EXT_PAGE(pll);=0A= +=0A= + /*=0A= + * These are debug registers, which the enable and disable=0A= + * sequences only touch with the EXT page's debug window=0A= + * open; read them the same way.=0A= + */=0A= + rc =3D sit9531x_write_u8(sitdev,=0A= + SIT9531X_REG(ext_page,=0A= + SIT9531X_PLL_REG_DEBUG),=0A= + SIT9531X_PLL_DEBUG_UNLOCK);=0A= + if (rc)=0A= + return rc;=0A= +=0A= + n_en =3D 0;=0A= + n_dis =3D 0;=0A= + for (i =3D 0; i < ARRAY_SIZE(intsync_config); i++) {=0A= + u16 reg;=0A= + u8 val;=0A= +=0A= + reg =3D SIT9531X_REG(ext_page, intsync_config[i].offset);=0A= +=0A= + rc =3D sit9531x_read_u8(sitdev, reg, &val);=0A= + if (rc)=0A= + break;=0A= + if (val =3D=3D intsync_config[i].en_val)=0A= + n_en++;=0A= + else if (val =3D=3D intsync_config[i].dis_val)=0A= + n_dis++;=0A= + }=0A= +=0A= + ret =3D sit9531x_intsync_debug_lock(sitdev, ext_page);=0A= + if (!rc)=0A= + rc =3D ret;=0A= + if (rc)=0A= + return rc;=0A= +=0A= + if (n_en =3D=3D ARRAY_SIZE(intsync_config)) {=0A= + /*=0A= + * Only one PLL can drive the net. If a second=0A= + * one matches, the registers are not describing=0A= + * a state this driver put the device in, so say=0A= + * so rather than pick silently.=0A= + */=0A= + if (src < 0)=0A= + src =3D pll;=0A= + else=0A= + dev_warn(sitdev->dev,=0A= + "PLL%c also matches the INTSYNC source pattern; keeping PLL%c\n",=0A= + 'A' + pll, 'A' + src);=0A= + } else if (n_en && n_dis &&=0A= + n_en + n_dis =3D=3D ARRAY_SIZE(intsync_config) &&=0A= + partial < 0) {=0A= + /*=0A= + * Every register holds one of the two patterns and both=0A= + * occur: the residue of an enable or a disable that=0A= + * stopped part way, and nothing a profile writes.=0A= + */=0A= + partial =3D pll;=0A= + }=0A= + }=0A= +=0A= + /*=0A= + * An enable or a disable that stopped part way leaves a PLL holding=0A= + * a mix of the two patterns. Treat it as the owner, so that another=0A= + * PLL cannot be enabled on top of the leftover configuration, but=0A= + * record that it is partial: a repeated connect on that PLL must run=0A= + * the enable again rather than take the PLL for configured, and a=0A= + * repeated disconnect runs the disable again.=0A= + */=0A= + sitdev->intsync_partial =3D src < 0 && partial >=3D 0;=0A= + if (sitdev->intsync_partial) {=0A= + dev_warn(sitdev->dev,=0A= + "PLL%c holds a partial INTSYNC source configuration\n",=0A= + 'A' + partial);=0A= + src =3D partial;=0A= + }=0A= +=0A= + sitdev->intsync_src =3D src;=0A= +=0A= + return 0;=0A= +}=0A= +=0A= +static int __sit9531x_intsync_disable(struct sit9531x_dev *sitdev,=0A= + u8 src_pll_idx, bool restore);=0A= +=0A= +/*=0A= + * sit9531x_intsync_enable - enable inter-PLL synchronization=0A= + * @src_pll_idx: source (frequency) PLL index (0-3)=0A= + *=0A= + * Enables INTSYNC global bit, unlocks the source PLL's EXT page=0A= + * debug registers, writes configuration, and triggers a small=0A= + * update on the source PLL.=0A= + *=0A= + * Caller must hold sitdev->multiop_lock.=0A= + */=0A= +int sit9531x_intsync_enable(struct sit9531x_dev *sitdev, u8 src_pll_idx)= =0A= +{=0A= + u8 ext_page, val;=0A= + int rc, lock_rc;=0A= + unsigned int i;=0A= +=0A= + lockdep_assert_held(&sitdev->multiop_lock);=0A= +=0A= + if (src_pll_idx >=3D SIT9531X_NUM_PLLS)=0A= + return -EINVAL;=0A= +=0A= + ext_page =3D SIT9531X_PLL_EXT_PAGE(src_pll_idx);=0A= +=0A= + rc =3D sit9531x_read_u8(sitdev, SIT9531X_REG_INTSYNC_GLOBAL, &val);=0A= + if (rc)=0A= + return rc;=0A= + rc =3D sit9531x_write_u8(sitdev, SIT9531X_REG_INTSYNC_GLOBAL,=0A= + val | BIT(SIT9531X_INTSYNC_EN_BIT));=0A= + if (rc)=0A= + return rc;=0A= +=0A= + /* Small update on Page 0 */=0A= + rc =3D sit9531x_write_u8(sitdev, SIT9531X_REG_GLOBAL_UPDATE,=0A= + SIT9531X_SMALL_UPDATE_CMD);=0A= + usleep_range(1000, 2000);=0A= + if (rc)=0A= + goto relock_err;=0A= +=0A= + /* Unlock debug on EXT page */=0A= + rc =3D sit9531x_write_u8(sitdev,=0A= + SIT9531X_REG(ext_page,=0A= + SIT9531X_PLL_REG_DEBUG),=0A= + SIT9531X_PLL_DEBUG_UNLOCK);=0A= + if (rc)=0A= + goto relock_err;=0A= +=0A= + for (i =3D 0; i < ARRAY_SIZE(intsync_config); i++) {=0A= + rc =3D sit9531x_write_u8(sitdev,=0A= + SIT9531X_REG(ext_page,=0A= + intsync_config[i].offset),=0A= + intsync_config[i].en_val);=0A= + if (rc)=0A= + goto relock_err;=0A= + }=0A= +=0A= + /* Small update on source PLL */=0A= + rc =3D sit9531x_pll_small_update(sitdev, src_pll_idx);=0A= + if (rc)=0A= + goto relock_err;=0A= +=0A= + rc =3D 0;=0A= + goto relock;=0A= +=0A= +relock_err:=0A= + sit9531x_intsync_debug_lock(sitdev, ext_page);=0A= + goto err_disable;=0A= +=0A= +relock:=0A= + /*=0A= + * Close the EXT page debug window the sequence opened. Nothing=0A= + * else writes the key back, so leaving it open would keep the block=0A= + * unlocked for as long as the device runs. The net is driven by=0A= + * now, though, so a failure here must not read as a failed enable:=0A= + * the caller would then not record the owner of a net that is=0A= + * driven.=0A= + */=0A= + lock_rc =3D sit9531x_intsync_debug_lock(sitdev, ext_page);=0A= + if (lock_rc)=0A= + dev_warn(sitdev->dev,=0A= + "PLL%c: INTSYNC enabled but the debug window was left open: %d\n",=0A= + 'A' + src_pll_idx, lock_rc);=0A= +=0A= + return rc;=0A= +=0A= +err_disable:=0A= + /*=0A= + * The global enable is already set at this point. The caller only=0A= + * records the source PLL when this function succeeds, so nothing=0A= + * else will ever clear the bit: undo it here rather than leave the=0A= + * net asserted with a half-written EXT page. The disable must not=0A= + * put the bit back when it fails part way, as it does for a=0A= + * disconnect: here the bit is what the rollback set out to clear,=0A= + * and restoring it would leave the net asserted with no PLL=0A= + * matching the source pattern, which no owner on record would ever=0A= + * clear.=0A= + */=0A= + {=0A= + int rollback_rc;=0A= +=0A= + rollback_rc =3D __sit9531x_intsync_disable(sitdev, src_pll_idx,=0A= + false);=0A= + if (rollback_rc)=0A= + dev_warn(sitdev->dev,=0A= + "INTSYNC rollback failed after enable error: %d (original %d)\n",=0A= + rollback_rc, rc);=0A= + }=0A= +=0A= + return rc;=0A= +}=0A= +=0A= +/*=0A= + * The disable sequence. @restore says whether a failure before the EXT= =0A= + * page holds the disable pattern puts the global enable back, which a=0A= + * disconnect wants (see restore_global below) and the rollback of a=0A= + * failed enable does not.=0A= + */=0A= +static int __sit9531x_intsync_disable(struct sit9531x_dev *sitdev,=0A= + u8 src_pll_idx, bool restore)=0A= +{=0A= + u8 ext_page, val;=0A= + int rc, lock_rc;=0A= + unsigned int i;=0A= +=0A= + lockdep_assert_held(&sitdev->multiop_lock);=0A= +=0A= + if (src_pll_idx >=3D SIT9531X_NUM_PLLS)=0A= + return -EINVAL;=0A= +=0A= + ext_page =3D SIT9531X_PLL_EXT_PAGE(src_pll_idx);=0A= +=0A= + rc =3D sit9531x_read_u8(sitdev, SIT9531X_REG_INTSYNC_GLOBAL, &val);=0A= + if (rc)=0A= + return rc;=0A= + rc =3D sit9531x_write_u8(sitdev, SIT9531X_REG_INTSYNC_GLOBAL,=0A= + val & ~BIT(SIT9531X_INTSYNC_EN_BIT));=0A= + if (rc)=0A= + goto restore_global;=0A= +=0A= + /* Small update on Page 0 */=0A= + rc =3D sit9531x_write_u8(sitdev, SIT9531X_REG_GLOBAL_UPDATE,=0A= + SIT9531X_SMALL_UPDATE_CMD);=0A= + usleep_range(1000, 2000);=0A= + if (rc)=0A= + goto restore_global;=0A= +=0A= + /* Unlock debug on EXT page */=0A= + rc =3D sit9531x_write_u8(sitdev,=0A= + SIT9531X_REG(ext_page,=0A= + SIT9531X_PLL_REG_DEBUG),=0A= + SIT9531X_PLL_DEBUG_UNLOCK);=0A= + if (rc)=0A= + goto restore_global;=0A= +=0A= + for (i =3D 0; i < ARRAY_SIZE(intsync_config); i++) {=0A= + rc =3D sit9531x_write_u8(sitdev,=0A= + SIT9531X_REG(ext_page,=0A= + intsync_config[i].offset),=0A= + intsync_config[i].dis_val);=0A= + if (rc)=0A= + goto restore_global;=0A= + }=0A= +=0A= + /*=0A= + * Small update on source PLL. The global enable is latched off and=0A= + * every register holds the disable value by now, so the net is not=0A= + * driven whether or not this latch went through. Putting the bit=0A= + * back for a failure here would describe the net as driven with no=0A= + * PLL matching the source pattern: the detector would record no=0A= + * owner, and nothing would ever clear the bit.=0A= + */=0A= + rc =3D sit9531x_pll_small_update(sitdev, src_pll_idx);=0A= +=0A= + goto relock;=0A= +=0A= +restore_global:=0A= + /*=0A= + * The global enable was cleared first, so a failure here leaves the=0A= + * EXT page still holding the enable pattern with nothing pointing=0A= + * at it: the source detector keys on the global bit, would report=0A= + * the net as unowned, and a retry of the disable would then=0A= + * short-circuit. Put the bit back so the state stays one the=0A= + * driver can describe and the request can be repeated.=0A= + */=0A= + if (restore &&=0A= + !sit9531x_read_u8(sitdev, SIT9531X_REG_INTSYNC_GLOBAL, &val) &&=0A= + !sit9531x_write_u8(sitdev, SIT9531X_REG_INTSYNC_GLOBAL,=0A= + val | BIT(SIT9531X_INTSYNC_EN_BIT))) {=0A= + /*=0A= + * Every write of the global enable, here and in SiTime's=0A= + * sequences, is followed by the page-0 small update that=0A= + * applies it. Without it the bit would sit pending until=0A= + * an unrelated commit through the same update register=0A= + * applied it, re-asserting the net over a half-written=0A= + * EXT page with nobody having asked.=0A= + */=0A= + sit9531x_write_u8(sitdev, SIT9531X_REG_GLOBAL_UPDATE,=0A= + SIT9531X_SMALL_UPDATE_CMD);=0A= + usleep_range(1000, 2000);=0A= + }=0A= +=0A= +relock:=0A= + /*=0A= + * Close the EXT page debug window the sequence opened. After a=0A= + * disable that took effect, a failure here is a warning, for the=0A= + * same reason as in sit9531x_intsync_enable().=0A= + */=0A= + lock_rc =3D sit9531x_intsync_debug_lock(sitdev, ext_page);=0A= + if (lock_rc) {=0A= + if (rc)=0A= + dev_warn(sitdev->dev,=0A= + "PLL%c: debug window left open: %d\n",=0A= + 'A' + src_pll_idx, lock_rc);=0A= + else=0A= + dev_warn(sitdev->dev,=0A= + "PLL%c: INTSYNC disabled but the debug window was left open: %d\n",= =0A= + 'A' + src_pll_idx, lock_rc);=0A= + }=0A= +=0A= + return rc;=0A= +}=0A= +=0A= +/*=0A= + * sit9531x_intsync_disable - disable inter-PLL synchronization=0A= + * @src_pll_idx: source (frequency) PLL index (0-3)=0A= + *=0A= + * Clears INTSYNC global bit, writes disable values to the source=0A= + * PLL's EXT page, and triggers a small update.=0A= + *=0A= + * Caller must hold sitdev->multiop_lock.=0A= + */=0A= +int sit9531x_intsync_disable(struct sit9531x_dev *sitdev, u8 src_pll_idx)= =0A= +{=0A= + return __sit9531x_intsync_disable(sitdev, src_pll_idx, true);=0A= +}=0A= +=0A= /**=0A= * sit9531x_phase_offset_read - read phase difference via TDC=0A= * @sitdev: device pointer=0A= @@ -3678,6 +4053,15 @@ static int sit9531x_dev_state_fetch(struct sit9531x_= dev *sitdev)=0A= return rc;=0A= }=0A= =0A= + mutex_lock(&sitdev->multiop_lock);=0A= + rc =3D sit9531x_intsync_src_detect(sitdev);=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= + if (rc) {=0A= + dev_err(sitdev->dev,=0A= + "Failed to detect INTSYNC source: %d\n", rc);=0A= + return rc;=0A= + }=0A= +=0A= for (i =3D 0; i < sitdev->info->num_outputs; i++) {=0A= bool clamped;=0A= s32 phase_ps;=0A= @@ -4418,13 +4802,13 @@ static bool sit9531x_dpll_pin_is_registrable(struct= sit9531x_dpll *sitdpll,=0A= if (index =3D=3D SIT9531X_MAX_INPUTS)=0A= return true;=0A= if (index =3D=3D SIT9531X_INTSYNC_PIN_ID)=0A= - return false;=0A= + return true;=0A= =0A= return sit9531x_input_pin_is_registrable(sitdev, index);=0A= }=0A= =0A= if (index =3D=3D SIT9531X_INTSYNC_OUT_PIN_ID)=0A= - return false;=0A= + return true;=0A= =0A= if (index >=3D sitdev->info->num_outputs)=0A= return false;=0A= @@ -4860,8 +5244,34 @@ static int sit9531x_suspend(struct device *dev)=0A= static int sit9531x_resume(struct device *dev)=0A= {=0A= struct sit9531x_dev *sitdev =3D dev_get_drvdata(dev);=0A= + int rc;=0A= + u8 i;=0A= =0A= sit9531x_page_cache_drop(sitdev);=0A= +=0A= + /*=0A= + * A part that lost power across suspend comes back with its=0A= + * profile's INTSYNC routing and output mutes, not with what the=0A= + * caches say, and the poll watches neither. Read them back here;=0A= + * a cache that cannot be read is left for the getter's read-through.=0A= + * Nothing races this: the poll is parked and the IRQ disabled.=0A= + */=0A= + mutex_lock(&sitdev->multiop_lock);=0A= + rc =3D sit9531x_intsync_src_detect(sitdev);=0A= + if (rc)=0A= + dev_warn(sitdev->dev,=0A= + "INTSYNC source not re-detected on resume: %d\n", rc);=0A= + for (i =3D 0; i < sitdev->info->num_outputs; i++) {=0A= + rc =3D sit9531x_output_state_refresh(sitdev, i);=0A= + if (rc) {=0A= + dev_warn(sitdev->dev,=0A= + "Output %u mute state not read on resume: %d\n",=0A= + i, rc);=0A= + sitdev->out[i].state_stale =3D true;=0A= + }=0A= + }=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= +=0A= if (sitdev->irq > 0)=0A= enable_irq(sitdev->irq);=0A= kthread_queue_delayed_work(sitdev->kworker, &sitdev->work, 0);=0A= diff --git a/drivers/dpll/sit9531x/core.h b/drivers/dpll/sit9531x/core.h=0A= index 1ed20354f94d..a5b343033a41 100644=0A= --- a/drivers/dpll/sit9531x/core.h=0A= +++ b/drivers/dpll/sit9531x/core.h=0A= @@ -211,6 +211,9 @@ struct sit9531x_chan {=0A= * I2C client), 0 if no IRQ is wired=0A= * @intsync_src: PLL index currently sourcing inter-PLL=0A= * synchronization (INTSYNC), or -1 when disabled=0A= + * @intsync_partial: @intsync_src holds only part of the source=0A= + * configuration, left by an enable or a disable=0A= + * that stopped part way=0A= * @irq_ack_fails: consecutive failures to acknowledge the=0A= * notification latches from the interrupt handler=0A= * @fvco_band_warned: bit per PLL whose Fref * DIVN has been reported as= =0A= @@ -248,6 +251,7 @@ struct sit9531x_dev {=0A= =0A= /* Inter-PLL synchronization state */=0A= s8 intsync_src;=0A= + bool intsync_partial;=0A= =0A= };=0A= =0A= @@ -308,6 +312,9 @@ int sit9531x_output_phase_adjust_set(struct sit9531x_de= v *sitdev,=0A= int sit9531x_clear_notifications(struct sit9531x_dev *sitdev);=0A= =0A= /* ---- INTSYNC (inter-PLL synchronization) ---- */=0A= +int sit9531x_intsync_enable(struct sit9531x_dev *sitdev, u8 src_pll_idx);= =0A= +int sit9531x_intsync_disable(struct sit9531x_dev *sitdev, u8 src_pll_idx);= =0A= +int sit9531x_intsync_src_detect(struct sit9531x_dev *sitdev);=0A= =0A= /* ---- Phase offset (TDC readback) ---- */=0A= int sit9531x_chan_routed_ref_read(struct sit9531x_dev *sitdev, u8 pll_idx,= =0A= diff --git a/drivers/dpll/sit9531x/dpll.c b/drivers/dpll/sit9531x/dpll.c=0A= index aab5a4f0f946..4c86ee9e7980 100644=0A= --- a/drivers/dpll/sit9531x/dpll.c=0A= +++ b/drivers/dpll/sit9531x/dpll.c=0A= @@ -27,6 +27,20 @@ static bool sit9531x_dpll_is_input_pin(const struct sit9= 531x_dpll_pin *pin)=0A= return pin->dir =3D=3D DPLL_PIN_DIRECTION_INPUT;=0A= }=0A= =0A= +static bool=0A= +sit9531x_dpll_is_intsync_pin(const struct sit9531x_dpll_pin *pin)=0A= +{=0A= + return sit9531x_dpll_is_input_pin(pin) &&=0A= + pin->id =3D=3D SIT9531X_INTSYNC_PIN_ID;=0A= +}=0A= +=0A= +static bool=0A= +sit9531x_dpll_is_intsync_src_pin(const struct sit9531x_dpll_pin *pin)=0A= +{=0A= + return !sit9531x_dpll_is_input_pin(pin) &&=0A= + pin->id =3D=3D SIT9531X_INTSYNC_OUT_PIN_ID;=0A= +}=0A= +=0A= static bool=0A= sit9531x_dpll_is_xo_pin(const struct sit9531x_dpll_pin *pin)=0A= {=0A= @@ -311,6 +325,59 @@ sit9531x_dpll_selection_state_get(struct sit9531x_dev = *sitdev,=0A= *state =3D DPLL_PIN_STATE_DISCONNECTED;=0A= }=0A= =0A= +/*=0A= + * Does the device feed a locked PLL from the INTSYNC net?=0A= + *=0A= + * Caller must hold sitdev->multiop_lock.=0A= + */=0A= +static bool sit9531x_dpll_intsync_tracked(struct sit9531x_dev *sitdev)=0A= +{=0A= + const struct sit9531x_chan *chan;=0A= + u8 pll;=0A= +=0A= + lockdep_assert_held(&sitdev->multiop_lock);=0A= +=0A= + for (pll =3D 0; pll < SIT9531X_NUM_PLLS; pll++) {=0A= + chan =3D sit9531x_chan_state_get(sitdev, pll);=0A= + if (chan->routed_ref =3D=3D SIT9531X_INTSYNC_PIN_ID &&=0A= + chan->locked && !chan->ho_freeze)=0A= + return true;=0A= + }=0A= +=0A= + return false;=0A= +}=0A= +=0A= +/*=0A= + * Does a selection-role pin carry a signal? A physical input has the=0A= + * device's LOS monitor; the INTSYNC net has no monitor, and what stands i= n=0A= + * for one is the driver's record of a PLL driving it. A partial source= =0A= + * configuration does not count: the source pin reports it as no=0A= + * connection, and the net is not confirmed driven.=0A= + *=0A= + * Caller must hold sitdev->multiop_lock.=0A= + */=0A= +static bool=0A= +sit9531x_dpll_selection_no_signal(struct sit9531x_dev *sitdev, u8 pin_id)= =0A= +{=0A= + lockdep_assert_held(&sitdev->multiop_lock);=0A= +=0A= + if (pin_id =3D=3D SIT9531X_INTSYNC_PIN_ID) {=0A= + /*=0A= + * The driver knows the net is driven when it enabled the=0A= + * source itself or found the configuration it would have=0A= + * written. A profile can drive the net with a configuration=0A= + * of its own; then a PLL the device feeds from the net and=0A= + * holds locked is the evidence that the net carries a signal.=0A= + */=0A= + if (sitdev->intsync_src >=3D 0 && !sitdev->intsync_partial)=0A= + return false;=0A= + return !sit9531x_dpll_intsync_tracked(sitdev);=0A= + }=0A= +=0A= + return pin_id < sitdev->info->num_inputs &&=0A= + sit9531x_ref_state_get(sitdev, pin_id)->los;=0A= +}=0A= +=0A= /*=0A= * Is this the reference the PLL is tracking now? See the S && L && !N=0A= * predicate in the pin-state contract. This is also what gates the=0A= @@ -334,11 +401,10 @@ sit9531x_dpll_selection_active(struct sit9531x_dev *s= itdev,=0A= =0A= /*=0A= * Fed to the PLL is not locked to: the device names the source it=0A= - * routes, and a lane that lost its signal is one the PLL is about=0A= + * routes, and a source that lost its signal is one the PLL is about=0A= * to be moved off, whatever the lock bit still says.=0A= */=0A= - if (pin_id < sitdev->info->num_inputs &&=0A= - sit9531x_ref_state_get(sitdev, pin_id)->los)=0A= + if (sit9531x_dpll_selection_no_signal(sitdev, pin_id))=0A= return false;=0A= =0A= return true;=0A= @@ -364,12 +430,17 @@ sit9531x_dpll_selection_operstate_get(struct sit9531x= _dev *sitdev,=0A= return;=0A= }=0A= =0A= + /*=0A= + * Standby is a qualified source the PLL is not using. A net nobody=0A= + * drives is no more that than a lane in LOS is.=0A= + */=0A= + if (sit9531x_dpll_selection_no_signal(sitdev, pin_id)) {=0A= + *operstate =3D DPLL_PIN_OPERSTATE_NO_SIGNAL;=0A= + return;=0A= + }=0A= +=0A= if (pin_id < sitdev->info->num_inputs) {=0A= ref =3D sit9531x_ref_state_get(sitdev, pin_id);=0A= - if (ref->los) {=0A= - *operstate =3D DPLL_PIN_OPERSTATE_NO_SIGNAL;=0A= - return;=0A= - }=0A= if (ref->qual_fail) {=0A= *operstate =3D DPLL_PIN_OPERSTATE_QUAL_FAILED;=0A= return;=0A= @@ -869,8 +940,325 @@ sit9531x_dpll_output_pin_direction_get(const struct d= pll_pin *pin,=0A= enum dpll_pin_direction *direction,=0A= struct netlink_ext_ack *extack);=0A= =0A= +/*=0A= + * Does this PLL drive the INTSYNC net with a complete configuration?=0A= + * What the source pin reports as CONNECTED.=0A= + *=0A= + * Caller must hold sitdev->multiop_lock.=0A= + */=0A= +static bool=0A= +sit9531x_dpll_intsync_src_connected(const struct sit9531x_dev *sitdev,=0A= + const struct sit9531x_dpll *sitdpll)=0A= +{=0A= + return sitdev->intsync_src =3D=3D sitdpll->id && !sitdev->intsync_partial= ;=0A= +}=0A= +=0A= +static int=0A= +sit9531x_dpll_intsync_src_state_on_dpll_get(const struct dpll_pin *pin,=0A= + void *pin_priv,=0A= + const struct dpll_device *dpll,=0A= + void *dpll_priv,=0A= + enum dpll_pin_state *state,=0A= + struct netlink_ext_ack *extack)=0A= +{=0A= + struct sit9531x_dpll *sitdpll =3D dpll_priv;=0A= + struct sit9531x_dev *sitdev =3D sitdpll->dev;=0A= +=0A= + mutex_lock(&sitdev->multiop_lock);=0A= + if (sit9531x_dpll_intsync_src_connected(sitdev, sitdpll))=0A= + *state =3D DPLL_PIN_STATE_CONNECTED;=0A= + else=0A= + *state =3D DPLL_PIN_STATE_DISCONNECTED;=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= +=0A= + return 0;=0A= +}=0A= +=0A= +/*=0A= + * sit9531x_dpll_intsync_src_state_on_dpll_set - drive INTSYNC from a PLL= =0A= + *=0A= + * CONNECTED -> this PLL drives the INTSYNC net=0A= + * DISCONNECTED -> stop driving INTSYNC if this PLL drives it=0A= + *=0A= + * SELECTABLE is rejected: driving the net is an explicit output routing,= =0A= + * not an automatic-selection candidate, matching the regular output pin.= =0A= + */=0A= +static int=0A= +sit9531x_dpll_intsync_src_state_on_dpll_set(const struct dpll_pin *pin,=0A= + void *pin_priv,=0A= + const struct dpll_device *dpll,=0A= + void *dpll_priv,=0A= + enum dpll_pin_state state,=0A= + struct netlink_ext_ack *extack)=0A= +{=0A= + struct sit9531x_dpll_pin *dpin =3D pin_priv;=0A= + struct sit9531x_dpll *sitdpll =3D dpll_priv;=0A= + struct sit9531x_dev *sitdev =3D sitdpll->dev;=0A= + int rc =3D 0, detect_rc =3D 0;=0A= + bool changed =3D false;=0A= + bool was_connected, moved;=0A= + u8 hw_src;=0A= +=0A= + mutex_lock(&sitdev->multiop_lock);=0A= +=0A= + was_connected =3D sit9531x_dpll_intsync_src_connected(sitdev, sitdpll);= =0A= +=0A= + switch (state) {=0A= + case DPLL_PIN_STATE_CONNECTED:=0A= + /*=0A= + * A partial configuration on this PLL is not a connection:=0A= + * run the enable again so a retry after a failed one repairs=0A= + * the device instead of reporting success over it.=0A= + */=0A= + if (was_connected)=0A= + break;=0A= + if (sitdev->intsync_src >=3D 0 &&=0A= + sitdev->intsync_src !=3D sitdpll->id) {=0A= + NL_SET_ERR_MSG(extack,=0A= + "INTSYNC is already sourced by another PLL");=0A= + rc =3D -EBUSY;=0A= + break;=0A= + }=0A= + /*=0A= + * A PLL that already lists INTSYNC among its references must=0A= + * not also drive it: the destination side refuses the mirror=0A= + * of this, and without the check here the net could be routed=0A= + * back into the PLL feeding it.=0A= + */=0A= + hw_src =3D sit9531x_input_hw_src(SIT9531X_INTSYNC_PIN_ID);=0A= + if (sit9531x_input_prio_present(sitdev, sitdpll->id, hw_src)) {=0A= + NL_SET_ERR_MSG(extack,=0A= + "PLL selects INTSYNC as a reference; it cannot drive it");=0A= + rc =3D -EBUSY;=0A= + break;=0A= + }=0A= + rc =3D sit9531x_intsync_enable(sitdev, sitdpll->id);=0A= + changed =3D true;=0A= + break;=0A= + case DPLL_PIN_STATE_DISCONNECTED:=0A= + if (sitdev->intsync_src !=3D sitdpll->id)=0A= + break;=0A= + rc =3D sit9531x_intsync_disable(sitdev, sitdpll->id);=0A= + changed =3D true;=0A= + break;=0A= + default:=0A= + rc =3D -EINVAL;=0A= + break;=0A= + }=0A= +=0A= + /*=0A= + * Record what was done before confirming it, and only when this PLL=0A= + * actually changed: the core forwards a request for the state the=0A= + * pin is already in, and a DISCONNECTED on a PLL that never drove the=0A= + * net must not erase the owner. The refresh below leaves the cache=0A= + * untouched when a read fails, and a cache that wrongly says nobody=0A= + * drives the net would let a second PLL be configured to drive it.=0A= + */=0A= + if (changed && !rc) {=0A= + sitdev->intsync_src =3D state =3D=3D DPLL_PIN_STATE_CONNECTED ?=0A= + sitdpll->id : -1;=0A= + sitdev->intsync_partial =3D false;=0A= + }=0A= +=0A= + /*=0A= + * Re-scan hardware after a transition so the cache follows a=0A= + * partially failed enable or disable as closely as possible.=0A= + */=0A= + if (changed)=0A= + detect_rc =3D sit9531x_intsync_src_detect(sitdev);=0A= + /*=0A= + * A failed enable that the scan still finds on this PLL is partial=0A= + * even when every register reads the enable pattern: the small=0A= + * update that commits it may be the step that failed. Mark it, so=0A= + * a retried connect runs the enable again.=0A= + *=0A= + * When the scan itself failed, nothing says how far the enable and=0A= + * its rollback got, and the net may be driven. Record this PLL as=0A= + * the partial owner rather than leave the cache saying nobody drives=0A= + * the net, which would let a second PLL be configured on top of it.=0A= + * A disconnect on this PLL runs the disable and a scan that settle=0A= + * the record.=0A= + */=0A= + if (changed && rc && state =3D=3D DPLL_PIN_STATE_CONNECTED &&=0A= + (detect_rc || sitdev->intsync_src =3D=3D sitdpll->id)) {=0A= + sitdev->intsync_src =3D sitdpll->id;=0A= + sitdev->intsync_partial =3D true;=0A= + }=0A= + /*=0A= + * The refresh only re-reads what the device now shows. Failing=0A= + * the request because that read hit a bus error would tell=0A= + * userspace the enable did not happen when it did.=0A= + */=0A= + if (detect_rc)=0A= + dev_warn(sitdev->dev,=0A= + "INTSYNC source cache not refreshed: %d\n",=0A= + detect_rc);=0A= +=0A= + /*=0A= + * What the pin reports may have moved although the request failed:=0A= + * a disable that stopped at its last step leaves nothing driving=0A= + * the net, a failed enable leaves a partial owner. The core=0A= + * notifies only a request that succeeded and the poll does not=0A= + * watch this pin, so announce it here, as the output setter does.=0A= + */=0A= + moved =3D sit9531x_dpll_intsync_src_connected(sitdev, sitdpll) !=3D=0A= + was_connected;=0A= +=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= +=0A= + if (rc) {=0A= + struct dpll_pin *dpll_pin;=0A= +=0A= + if (rc !=3D -EBUSY && rc !=3D -EINVAL && rc !=3D -EOPNOTSUPP)=0A= + NL_SET_ERR_MSG(extack,=0A= + "Failed to set INTSYNC source state");=0A= + /*=0A= + * The core's lock is held here, as the helper requires.=0A= + * Teardown clears the handle before it unregisters the pin;=0A= + * see the output state setter.=0A= + */=0A= + dpll_pin =3D READ_ONCE(dpin->dpll_pin);=0A= + if (moved && dpll_pin)=0A= + __dpll_pin_change_ntf(dpll_pin);=0A= + }=0A= +=0A= + return rc;=0A= +}=0A= +=0A= +static const struct dpll_pin_ops sit9531x_dpll_intsync_src_pin_ops =3D {= =0A= + .direction_get =3D sit9531x_dpll_output_pin_direction_get,=0A= + .state_on_dpll_get =3D sit9531x_dpll_intsync_src_state_on_dpll_get,=0A= + .state_on_dpll_set =3D sit9531x_dpll_intsync_src_state_on_dpll_set,=0A= +};=0A= +=0A= /* ---- INTSYNC destination (input) pin ---- */=0A= =0A= +/*=0A= + * sit9531x_dpll_intsync_dst_state_on_dpll_get - INTSYNC reference state= =0A= + *=0A= + * Selection role, so the contract above decides this exactly as it does= =0A= + * for a physical input: the priority table is the eligibility record, and= =0A= + * whether a source PLL happens to be driving the net right now is no more= =0A= + * a state than a momentary LOS is on an external reference. The one=0A= + * addition is that the PLL driving INTSYNC is never its own destination.= =0A= + */=0A= +static int=0A= +sit9531x_dpll_intsync_dst_state_on_dpll_get(const struct dpll_pin *pin,=0A= + void *pin_priv,=0A= + const struct dpll_device *dpll,=0A= + void *dpll_priv,=0A= + enum dpll_pin_state *state,=0A= + struct netlink_ext_ack *extack)=0A= +{=0A= + struct sit9531x_dpll *sitdpll =3D dpll_priv;=0A= + struct sit9531x_dev *sitdev =3D sitdpll->dev;=0A= +=0A= + mutex_lock(&sitdev->multiop_lock);=0A= + if (sitdev->intsync_src =3D=3D sitdpll->id)=0A= + *state =3D DPLL_PIN_STATE_DISCONNECTED;=0A= + else=0A= + sit9531x_dpll_selection_state_get(sitdev, sitdpll,=0A= + SIT9531X_INTSYNC_PIN_ID,=0A= + state);=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= +=0A= + return 0;=0A= +}=0A= +=0A= +/*=0A= + * sit9531x_dpll_intsync_dst_state_on_dpll_set - lock a PLL to INTSYNC=0A= + *=0A= + * Selection role, so this accepts and refuses what a physical input does,= =0A= + * CONNECTED included: the device pins no reference on request whichever= =0A= + * source is asked for. INTSYNC is an internal net with no physical=0A= + * receiver, so only the per-PLL priority table is touched; the source pin= =0A= + * controls generation.=0A= + */=0A= +static int=0A= +sit9531x_dpll_intsync_dst_state_on_dpll_set(const struct dpll_pin *pin,=0A= + void *pin_priv,=0A= + const struct dpll_device *dpll,=0A= + void *dpll_priv,=0A= + enum dpll_pin_state state,=0A= + struct netlink_ext_ack *extack)=0A= +{=0A= + struct sit9531x_dpll *sitdpll =3D dpll_priv;=0A= + struct sit9531x_dev *sitdev =3D sitdpll->dev;=0A= + u8 hw_src =3D sit9531x_input_hw_src(SIT9531X_INTSYNC_PIN_ID);=0A= + int rc;=0A= +=0A= + mutex_lock(&sitdev->multiop_lock);=0A= +=0A= + switch (state) {=0A= + case DPLL_PIN_STATE_DISCONNECTED:=0A= + rc =3D sit9531x_input_prio_remove(sitdev, sitdpll->id, hw_src);=0A= + break;=0A= + case DPLL_PIN_STATE_CONNECTED:=0A= + NL_SET_ERR_MSG(extack,=0A= + "Device selects its reference by priority; use selectable");=0A= + rc =3D -EOPNOTSUPP;=0A= + break;=0A= + case DPLL_PIN_STATE_SELECTABLE:=0A= + if (sitdev->intsync_src =3D=3D sitdpll->id) {=0A= + NL_SET_ERR_MSG(extack,=0A= + "PLL cannot lock to the INTSYNC it drives");=0A= + rc =3D -EINVAL;=0A= + break;=0A= + }=0A= + rc =3D sit9531x_input_prio_add(sitdev, sitdpll->id, hw_src);=0A= + break;=0A= + default:=0A= + rc =3D -EINVAL;=0A= + break;=0A= + }=0A= +=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= +=0A= + if (rc =3D=3D -ENOSPC)=0A= + NL_SET_ERR_MSG(extack,=0A= + "Priority table is full of unique sources on this PLL");=0A= + else if (rc && rc !=3D -EINVAL && rc !=3D -EOPNOTSUPP)=0A= + NL_SET_ERR_MSG(extack, "Failed to set INTSYNC input state");=0A= +=0A= + return rc;=0A= +}=0A= +=0A= +static int=0A= +sit9531x_dpll_intsync_dst_operstate_on_dpll_get(const struct dpll_pin *pin= ,=0A= + void *pin_priv,=0A= + const struct dpll_device *dpll,=0A= + void *dpll_priv,=0A= + enum dpll_pin_operstate *state,=0A= + struct netlink_ext_ack *extack)=0A= +{=0A= + struct sit9531x_dpll *sitdpll =3D dpll_priv;=0A= + struct sit9531x_dev *sitdev =3D sitdpll->dev;=0A= +=0A= + mutex_lock(&sitdev->multiop_lock);=0A= + sit9531x_dpll_selection_operstate_get(sitdev, sitdpll,=0A= + SIT9531X_INTSYNC_PIN_ID,=0A= + state);=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= +=0A= + return 0;=0A= +}=0A= +=0A= +/*=0A= + * Do not add .frequency_get / the generic input state getter here: the=0A= + * destination pin id is SIT9531X_INTSYNC_PIN_ID, one past the end of the= =0A= + * ref[] array (INTSYNC is an internal net with no ref[] entry). The ops= =0A= + * below only ever key on chan[] and the priority table, never ref[id].=0A= + */=0A= +static const struct dpll_pin_ops sit9531x_dpll_intsync_dst_pin_ops =3D {= =0A= + .direction_get =3D sit9531x_dpll_input_pin_direction_get,=0A= + .state_on_dpll_get =3D sit9531x_dpll_intsync_dst_state_on_dpll_get,=0A= + .state_on_dpll_set =3D sit9531x_dpll_intsync_dst_state_on_dpll_set,=0A= + .operstate_on_dpll_get =3D=0A= + sit9531x_dpll_intsync_dst_operstate_on_dpll_get,=0A= + .prio_get =3D sit9531x_dpll_input_pin_prio_get,=0A= + .prio_set =3D sit9531x_dpll_input_pin_prio_set,=0A= +};=0A= +=0A= /*=0A= * XO (crystal oscillator) pin ops=0A= *=0A= @@ -1197,8 +1585,13 @@ static const struct dpll_pin_ops sit9531x_dpll_outpu= t_pin_ops =3D {=0A= const struct dpll_pin_ops *=0A= sit9531x_dpll_pin_ops_get(const struct sit9531x_dpll_pin *pin)=0A= {=0A= - if (!sit9531x_dpll_is_input_pin(pin))=0A= + if (!sit9531x_dpll_is_input_pin(pin)) {=0A= + if (sit9531x_dpll_is_intsync_src_pin(pin))=0A= + return &sit9531x_dpll_intsync_src_pin_ops;=0A= return &sit9531x_dpll_output_pin_ops;=0A= + }=0A= + if (sit9531x_dpll_is_intsync_pin(pin))=0A= + return &sit9531x_dpll_intsync_dst_pin_ops;=0A= if (sit9531x_dpll_is_xo_pin(pin))=0A= return &sit9531x_dpll_xo_pin_ops;=0A= /*=0A= diff --git a/drivers/dpll/sit9531x/regs.h b/drivers/dpll/sit9531x/regs.h=0A= index 1891679698e2..601dafbb2179 100644=0A= --- a/drivers/dpll/sit9531x/regs.h=0A= +++ b/drivers/dpll/sit9531x/regs.h=0A= @@ -312,6 +312,9 @@=0A= #define SIT9531X_PLL_REG_ACTIVE 0x02=0A= #define SIT9531X_PLL_ACTIVE_BIT BIT(0) /* PLL reached active state */=0A= =0A= +/* PLL EXT page INTSYNC configuration registers */=0A= +#define SIT9531X_PLL_EXT_PAGE(_idx) (SIT9531X_PAGE_PLLA_EXT + (_idx))=0A= +=0A= #define SIT9531X_PLL_STATUS_OUTER_DIS BIT(5)=0A= =0A= /*=0A= -- =0A= 2.39.2 (Apple Git-143)=0A= =0A=