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Add a binding for the SiTime SiT9531x family of clock generators: an=0A= I2C-controlled device with four independent PLLs, up to eight input=0A= clocks and up to twelve outputs, described as a DPLL provider.=0A= =0A= The XO is given either as a clock or, for firmware that describes the=0A= oscillator as a property rather than as a clock provider, such as ACPI,=0A= as clock-frequency.=0A= =0A= The supplies are described by their pin names: the core and input rails,=0A= the GPIO rail the SiT95317 has, and one per output-driver pin -- VDDO0 to= =0A= VDDO7 on the SiT95317, VDDO0_1, VDDO2 to VDDO9 and VDDO10_11 on the=0A= SiT95316. The driver does not enable them, since the boards so far=0A= power the part permanently; describing them gives a board with=0A= switchable rails a way to say so.=0A= =0A= Signed-off-by: Ali Rouhi =0A= ---=0A= .../bindings/dpll/sitime,sit95316.yaml | 213 ++++++++++++++++++=0A= MAINTAINERS | 6 +=0A= 2 files changed, 219 insertions(+)=0A= create mode 100644 Documentation/devicetree/bindings/dpll/sitime,sit95316.= yaml=0A= =0A= diff --git a/Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml b/= Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml=0A= new file mode 100644=0A= index 000000000000..200b9f709a57=0A= --- /dev/null=0A= +++ b/Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml=0A= @@ -0,0 +1,213 @@=0A= +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)=0A= +%YAML 1.2=0A= +---=0A= +$id: http://devicetree.org/schemas/dpll/sitime,sit95316.yaml#=0A= +$schema: http://devicetree.org/meta-schemas/core.yaml#=0A= +=0A= +title: SiTime SiT95316/SiT95317 DPLL Clock Generator=0A= +=0A= +maintainers:=0A= + - Ali Rouhi =0A= +=0A= +description: |=0A= + SiTime SiT95316 and SiT95317 are I2C-controlled programmable clock=0A= + generators with integrated DPLL for synchronization applications. Both= =0A= + variants contain four PLLs with automatic/manual reference selection,=0A= + DCO frequency adjustment, and phase offset measurement via an on-chip=0A= + TDC (Time-to-Digital Converter).=0A= +=0A= + Both parts have 4 differential input pairs whose lanes can also be=0A= + driven independently as single-ended references, so 8 inputs are=0A= + individually selectable. SiT95317 drives 8 outputs, SiT95316=0A= + drives 12.=0A= +=0A= + Pin numbering. An input pin's reg is its lane: 2k is INkP and 2k + 1=0A= + is INkN, 0 to 7. A pair the loaded configuration runs differential is= =0A= + one input, described at 2k. An output pin's reg is its physical output= =0A= + OUTn, 0 to 11; the SiT95317 bonds out OUT0, OUT3, OUT4, OUT5, OUT7, OUT8= ,=0A= + OUT9 and OUT11.=0A= +=0A= +properties:=0A= + compatible:=0A= + enum:=0A= + - sitime,sit95316=0A= + - sitime,sit95317=0A= +=0A= + reg:=0A= + maxItems: 1=0A= +=0A= + clocks:=0A= + maxItems: 1=0A= +=0A= + clock-names:=0A= + items:=0A= + - const: xtal=0A= +=0A= + clock-frequency:=0A= + description:=0A= + XO rate in Hz feeding XIN/XO_CLK, for firmware that describes the=0A= + oscillator as a property rather than as a clock provider, such as=0A= + ACPI. Use either this or "clocks", not both.=0A= +=0A= + reset-gpios:=0A= + maxItems: 1=0A= + description:=0A= + GPIO connected to the chip's active-low reset pin (RESETB).=0A= +=0A= + interrupts:=0A= + maxItems: 1=0A= + description:=0A= + Interrupt from the chip's active-low INTRB output. Asserted when=0A= + the device detects a status change such as lock acquisition or loss.= =0A= +=0A= + dpll-types:=0A= + maxItems: 4=0A= +=0A= + vdd-supply:=0A= + description: Core supply of the PLLs, 1.8 V (the VDD pins).=0A= +=0A= + vddin-supply:=0A= + description:=0A= + Supply of the input receivers and dividers, 3.3 V (VDDIN).=0A= +=0A= + vdds-supply:=0A= + description:=0A= + Supply of the two GPIO pins that have their own rail (VDDS). The=0A= + SiT95316 has no such pin.=0A= +=0A= + input-pins:=0A= + type: object=0A= + patternProperties:=0A= + "^pin@[0-9a-f]+$":=0A= + type: object=0A= + properties:=0A= + reg:=0A= + maximum: 7=0A= +=0A= + supported-frequencies-hz:=0A= + description:=0A= + The rate wired to the input, in Hz, as a single entry. An= =0A= + input runs at the rate the board feeds it and has no=0A= + frequency to select, so that entry is what the pin reports= =0A= + as its frequency.=0A= +=0A= +patternProperties:=0A= + "^vddo([0-9]|1[01]|0_1|10_11)-supply$":=0A= + description: |=0A= + Supply of an output driver, named after its VDDO pin. The SiT95317= =0A= + has one per output, VDDO0 to VDDO7, numbered as that part's=0A= + datasheet numbers its outputs; in the pin numbering of this binding= =0A= + those are outputs 0, 3, 4, 5, 7, 8, 9 and 11, in that order. The=0A= + SiT95316 has VDDO0_1, VDDO2 to VDDO9 and VDDO10_11, the two shared= =0A= + pins each powering the pair of outputs they are named after.=0A= +=0A= +required:=0A= + - compatible=0A= + - reg=0A= +=0A= +dependencies:=0A= + clocks: [ clock-names ]=0A= +=0A= +oneOf:=0A= + - required:=0A= + - clocks=0A= + - required:=0A= + - clock-frequency=0A= +=0A= +allOf:=0A= + - $ref: /schemas/dpll/dpll-device.yaml#=0A= + - if:=0A= + properties:=0A= + compatible:=0A= + const: sitime,sit95317=0A= + then:=0A= + properties:=0A= + output-pins:=0A= + patternProperties:=0A= + "^pin@[0-9a-f]+$":=0A= + properties:=0A= + reg:=0A= + enum: [0, 3, 4, 5, 7, 8, 9, 11]=0A= + patternProperties:=0A= + "^vddo(8|9|1[01]|0_1|10_11)-supply$": false=0A= + else:=0A= + properties:=0A= + vdds-supply: false=0A= + output-pins:=0A= + patternProperties:=0A= + "^pin@[0-9a-f]+$":=0A= + properties:=0A= + reg:=0A= + maximum: 11=0A= + patternProperties:=0A= + "^vddo(1[01]|[01])-supply$": false=0A= +=0A= +unevaluatedProperties: false=0A= +=0A= +examples:=0A= + - |=0A= + #include =0A= + #include =0A= +=0A= + i2c {=0A= + #address-cells =3D <1>;=0A= + #size-cells =3D <0>;=0A= +=0A= + dpll@68 {=0A= + compatible =3D "sitime,sit95316";=0A= + reg =3D <0x68>;=0A= + clocks =3D <&xo2>;=0A= + clock-names =3D "xtal";=0A= + reset-gpios =3D <&gpio 78 GPIO_ACTIVE_LOW>;=0A= + interrupts =3D <12 IRQ_TYPE_LEVEL_LOW>;=0A= + vdd-supply =3D <®_1v8>;=0A= + vddin-supply =3D <®_3v3>;=0A= + vddo0_1-supply =3D <®_3v3>;=0A= + vddo10_11-supply =3D <®_1v8>;=0A= + dpll-types =3D "eec", "eec", "eec", "eec";=0A= +=0A= + input-pins {=0A= + #address-cells =3D <1>;=0A= + #size-cells =3D <0>;=0A= +=0A= + /* IN0P and IN0N: pair 0 runs single-ended */=0A= + pin@0 {=0A= + reg =3D <0>;=0A= + label =3D "clkin0";=0A= + connection-type =3D "ext";=0A= + supported-frequencies-hz =3D /bits/ 64 <10000000>;=0A= + };=0A= +=0A= + pin@1 {=0A= + reg =3D <1>;=0A= + label =3D "clkin1";=0A= + connection-type =3D "synce";=0A= + supported-frequencies-hz =3D /bits/ 64 <156250000>;=0A= + };=0A= + };=0A= +=0A= + output-pins {=0A= + #address-cells =3D <1>;=0A= + #size-cells =3D <0>;=0A= +=0A= + pin@0 {=0A= + reg =3D <0>;=0A= + label =3D "clkout0";=0A= + supported-frequencies-hz =3D /bits/ 64 <156250000>;=0A= + };=0A= +=0A= + pin@1 {=0A= + reg =3D <1>;=0A= + label =3D "clkout1";=0A= + supported-frequencies-hz =3D /bits/ 64 <25000000>;=0A= + };=0A= +=0A= + pin@a {=0A= + reg =3D <10>;=0A= + label =3D "clkout10";=0A= + supported-frequencies-hz =3D /bits/ 64 <10000000>;=0A= + };=0A= + };=0A= + };=0A= + };=0A= +...=0A= diff --git a/MAINTAINERS b/MAINTAINERS=0A= index 72ca3aab2106..858fe1c4332c 100644=0A= --- a/MAINTAINERS=0A= +++ b/MAINTAINERS=0A= @@ -25182,6 +25182,12 @@ S: Maintained=0A= W: http://www.winischhofer.at/linuxsisusbvga.shtml=0A= F: drivers/usb/misc/sisusbvga/=0A= =0A= +SITIME SIT9531X DPLL DRIVER=0A= +M: Ali Rouhi =0A= +L: netdev@vger.kernel.org=0A= +S: Maintained=0A= +F: Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml=0A= +=0A= SL28 CPLD MFD DRIVER=0A= M: Michael Walle =0A= S: Maintained=0A= -- =0A= 2.39.2 (Apple Git-143)=0A= =0A=