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Sat, 10 Oct 2026 10:59:36 +0000 From: Changhuang Liang To: Stephen Boyd , Brian Masney , Jerome Brunet , Philipp Zabel , Emil Renner Berthing Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Changhuang Liang , Hal Feng Subject: [PATCH v6 0/5] Add StarFive JHB100 syscon modules Date: Sat, 10 Oct 2026 03:58:54 -0700 Message-Id: <20261010105859.19505-1-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: ZQ0PR01CA0036.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:2::20) To NT0PR01MB1216.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:11::9) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: NT0PR01MB1216:EE_|NT0PR01MB1005:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e1b08b9-814e-437f-f3e7-08df26bd92c9 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|52116014|7416014|376014|23010399003|18002099003|10067099003|3023799007|261009223027099003|38350700014|56012099006; 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This series adds related drivers for PLL and reset. This series depends on the series: [1]: https://lore.kernel.org/all/20261008123338.11081-1-changhuang.liang@starfivetech.com/ changes since v5: - Remove PATCH 1/7/8 in v5 PATCH 1 (in v6): - Split a PLL into 3 clock modules: VCO, POSTDIV, and OUT. - Implement the PLL registration as a generic interface, provided for specific PLLs to call. - Since the PLL enable/disable function is optional, the new version decides to remove this implementation and keep the PLL always on. (This may differ from the email reply in v5.) - Remove the debugfs-related implementation. - Add a VCO operating frequency range limit for the PLL. - Stop recording the PLL frequency, and instead calculate it from the multiplier factor. PATCH 2&3(in v6): - Make corresponding adjustments due to the changes in PATCH 1. PATCH 5(in v6): Make minor adjustments due to the changes in series [1], with no functional changes: - select RESET_STARFIVE_COMMON ==> select RESET_STARFIVE_JH71X0 v5: https://lore.kernel.org/all/20260828095608.19955-1-changhuang.liang@starfivetech.com/ v4: https://lore.kernel.org/all/20260809015054.210577-1-changhuang.liang@starfivetech.com/ v3: https://lore.kernel.org/all/20260521012932.24163-1-changhuang.liang@starfivetech.com/ v2: https://lore.kernel.org/all/20260512083521.3448-1-changhuang.liang@starfivetech.com/ V1: https://lore.kernel.org/all/20260403054945.467700-1-changhuang.liang@starfivetech.com/ Changhuang Liang (5): clk: starfive: Add system-0 domain PLL clock driver clk: starfive: Add Peripheral-0 domain PLL clock driver clk: starfive: Add Peripheral-1 domain PLL clock driver reset: starfive: Introduce active_low reset: starfive: Add syscon reset driver support drivers/clk/starfive/Kconfig | 28 ++ drivers/clk/starfive/Makefile | 3 + .../starfive/clk-starfive-jhb100-per-pll.c | 95 ++++ .../clk/starfive/clk-starfive-jhb100-pll.c | 425 ++++++++++++++++++ .../clk/starfive/clk-starfive-jhb100-pll.h | 63 +++ .../starfive/clk-starfive-jhb100-sys0-pll.c | 69 +++ drivers/reset/starfive/Kconfig | 9 + drivers/reset/starfive/Makefile | 1 + .../reset/starfive/reset-starfive-jh71x0.c | 3 +- .../reset/starfive/reset-starfive-jh71x0.h | 6 + .../starfive/reset-starfive-jhb100-syscon.c | 61 +++ 11 files changed, 762 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per-pll.c create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-pll.c create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-pll.h create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys0-pll.c create mode 100644 drivers/reset/starfive/reset-starfive-jhb100-syscon.c -- 2.25.1