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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/8] dt-bindings: net: amlogic,meson-dwmac: add amlogic,t7-dwmac Date: Sat, 10 Oct 2026 11:58:54 +0100 Message-ID: <20261010105900.247342-3-tanure@linux.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261010105900.247342-1-tanure@linux.com> References: <20261010105900.247342-1-tanure@linux.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The T7 has the same ethernet glue as the G12A, but needs two clocks of its own. The controller reaches memory through a pipeline stage with a gate of its own; nothing else claims it, so it is switched off as unused and the port can no longer finish a transfer. The glue registers sit in a block clocked together with the MDIO multiplexer, which only probes after the controller has programmed them: with the clock still off those writes are lost, and the port keeps whatever delays the bootloader left behind. So the T7 gets its own clock list, without the timing adjustment clock it never uses. The delays follow ethernet-controller.yaml, so the vendor properties are not valid here. Assisted-by: LLM Signed-off-by: Lucas Tanure --- .../bindings/net/amlogic,meson-dwmac.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml index 90ef79161ab1..2353dd9181ed 100644 --- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml @@ -23,6 +23,7 @@ select: - amlogic,meson-gxbb-dwmac - amlogic,meson-axg-dwmac - amlogic,meson-g12a-dwmac + - amlogic,t7-dwmac required: - compatible @@ -57,6 +58,56 @@ allOf: - const: clkin1 - const: timing-adjustment + - if: + properties: + compatible: + contains: + const: amlogic,t7-dwmac + then: + properties: + clocks: + items: + - description: GMAC main clock + - description: First parent clock of the internal mux + - description: Second parent clock of the internal mux + - description: + clock of the pipeline stage inserted in the bus path between + the controller and the DRAM. Without it, the controller cannot + complete DMA transfers. + - description: + clock of the register block holding PRG_ETH0 and PRG_ETH1. + Without it, the block reads as zero and ignores writes. + + clock-names: + items: + - const: stmmaceth + - const: clkin0 + - const: clkin1 + - const: pipeline + - const: pclk + + # The TX delay is a quarter of the RGMII clock period per step, + # which is 2ns at 1Gbit/s. + tx-internal-delay-ps: + enum: [0, 2000, 4000, 6000] + default: 0 + + rx-internal-delay-ps: + default: 0 + + # Delay definitions for Meson8b and newer + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson8b-dwmac + - amlogic,meson8m2-dwmac + - amlogic,meson-gxbb-dwmac + - amlogic,meson-axg-dwmac + - amlogic,meson-g12a-dwmac + then: + properties: amlogic,tx-delay-ns: enum: [0, 2, 4, 6] default: 2 @@ -106,6 +157,7 @@ allOf: contains: enum: - amlogic,meson-g12a-dwmac + - amlogic,t7-dwmac then: properties: rx-internal-delay-ps: @@ -143,6 +195,10 @@ properties: - amlogic,meson6-dwmac - amlogic,meson8m2-dwmac - const: snps,dwmac + - items: + - const: amlogic,t7-dwmac + - const: snps,dwmac-5.10a + - const: snps,dwmac reg: items: -- 2.56.0