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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 7/8] arm64: dts: amlogic: t7: khadas-vim4: enable the ethernet port Date: Sat, 10 Oct 2026 11:58:59 +0100 Message-ID: <20261010105900.247342-8-tanure@linux.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261010105900.247342-1-tanure@linux.com> References: <20261010105900.247342-1-tanure@linux.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The board carries a Realtek RTL8211F gigabit PHY on the external management bus, connected to the MAC over RGMII. Enable the controller, hand it the ethernet pins and point it at the PHY. RGMII needs a delay on each of its two clocks, and on this board both come from inside the chips, not from the board traces. The PHY adds the one on receive. Its transmit delay does not work here, so the controller adds that one. The PHY interrupt output is wired to GPIOH_6, so link changes are reported instead of polled. The PHY reset is an RC network on the board, not a SoC pin, so there is no reset line to describe. Assisted-by: LLM Signed-off-by: Lucas Tanure --- .../amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts index 0fa83362b417..c18bde02ac40 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts @@ -14,6 +14,7 @@ / { compatible = "khadas,vim4", "amlogic,a311d2", "amlogic,t7"; aliases { + ethernet0 = ðmac; serial0 = &uart_a; mmc0 = &sd_emmc_c; mmc1 = &sd_emmc_b; @@ -256,6 +257,25 @@ xtal: xtal-clk { }; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-mode = "rgmii-id"; + phy-handle = <&external_phy>; + tx-internal-delay-ps = <2000>; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211FD-CG */ + reg = <0>; + + interrupt-parent = <&gpio_intc>; + interrupts = ; + }; +}; + &i2c_m_ao_a { status = "okay"; pinctrl-0 = <&i2c0_ao_d_pins>; -- 2.56.0