From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04799472536 for ; Mon, 12 Oct 2026 12:00:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791806409; cv=none; b=Pe40BX1sw+QyxP1CoHqFuVr4Us3nZX5s+e9kxSmyhiFnOvqF19TBFs6qbX3JF4llCwAhJqK60fdgd2t/sXfDCMZGkO6au9ljZocSFD+gJNSX/mhuBIc1eVmoi4S5KZWUVPr5YN1JIQb79gcgSlM4p1KQaWQzeBRYVh/eDqpX1ls= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791806409; c=relaxed/simple; bh=uJO0x+twjfdPvJ/0mT0DcGfA1b9Ep68ho2w3QISj/JE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KkoS/OiimL7TPU5/N/lWrwg2A6h3FQA62q/rWnw0Y27VL9I8HZhUdEfgHs8WSYnWbMH7y71icOmZI84fo2RtogCGNswdLmN01X40n7A2YpjTTZaXLo0o7winECxVQp8p79vGzGpvdM+TSm8A/onsMioR3fEvmmQ7Cj1WN5txXrQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=qWYT0ERS; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qWYT0ERS" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-48b0946c2c2so1004639f8f.3 for ; Mon, 12 Oct 2026 05:00:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1791806406; x=1792411206; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=WVzQlzuOAOAU8FqTRYUEu/wekejvB+QTicY0sP3NUzg=; b=qWYT0ERS4rXWH3v42Pfy/XSTPm5++Hd/ybiDJSeMCIUHyN1QlcBXB1g3JMhHTOeU95 Pr7LFaCAcqr6XX5DmhlQp/O3udyZHvb6ca2/TBedurJy4achrp+JjDr79uaVtBxsCfk/ RuDGR6dJx9lIB2Xgd5aZOWiEuOwDwGWBaGojqSf0hF+JVi5K9rZ5gBSqN9y8QORuWLaV lFT9guLirRn+SJ3v1sGNOjY4Q+2qJ5YSSw3Lp76+QMwtvF8CAvZ7X+eGxSb802V7mPQg CCjULn6ZZBFcWrM9dYaFAstcw3xIiKz2oqa5euDwoOn5KUZiSRm0f00iopJNhl4dVRl3 olTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1791806406; x=1792411206; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=WVzQlzuOAOAU8FqTRYUEu/wekejvB+QTicY0sP3NUzg=; b=DPWQ7BBGKS+k5QEZ4Aa93awgfYaWUJEwQn1NeWlgvTymMN/E/SAlzAqf3mSqhRCCt4 Gv64w95F4ps2PkQ2JDIQ40hISf+9qGSZKwRTMp6j7MqU5y9Wvyec8E+OIOZcusNSunt8 vzkMk07jFzKsoynlgtB3x3EkDpeAHK4ZYMFCB61IalN1Qu72RFyJQ6/oi0mTotxqv934 bKJEZ2FgiCLVMkzPiqsdbPq10eRDPO1li4BIM+VXXHep+iiBFzGA9HlAV4UUnqBhkmt3 /1YYkxNgNPCLxOToa9N149A2I8Jy7n8gzQJjqEoTJMv8zLpz29fwPF3kReRj9CsA+c0v JXMA== X-Forwarded-Encrypted: i=1; AKwUvBy42uzHTjy36q8RDlU83oReKjrK2mdDr5WHTlpwG8SJ4fJnx5RQmkj8ha0PPthh21qUE0MvgyoXvHVP@vger.kernel.org X-Gm-Message-State: AFq9FYK+sfD3YYeLXK0SNF1VKGAmBjKPWe1gD/JFV7cblPMA8TmjsUbD IEmkqE1SDv7CFM4xr19ywNep+bQiAGm0qD2C0zdOseGuUSff6epP4g+O X-Gm-Gg: AYBFou3hPu2tAQX7yYw4vqDwYl6gojXSzoft7Md1L2LupAx6PeTWhw8+55iiRWBLAQ2 aAR2LNzmlU7ymgRErQQLgxbEQElwsr0Rq9s+/3MC96C8zXcSLz5hio65Uwt7oL6yqlnNXrZ+L0i s2BGOpVa2kIX5nZ0LqvAypH5VO0wI/obFiTuF5v0wnwFebJ+HbhtVgv8UaR3b/oYKxKfpFyzPFo DH3E22KeG3qQcjE8iW33HImblXqn28i3tfncQkuBnM1nEQVKaH01mZNpT5zkyj9aE4+0EQ7I0cs Fz5dwo6GNBuZ3qSlIuh8hszKavmZKR5lHZ+4mUVDafduPPgwzKShYPyytLNwi5qxtaJfY6daWXo 9j9K4d4m5mZxMuDbvkyHFfjgs3XzxL8RBdTgkahWsuxL/OxjN9DSG1Noa663emkutOxOBpwM4yh y1TBGGFOwSVV4etMbnPxGHk5CmgmMtA9YW1TKO/ruKZgousF3kfChUcudTUizWiloNWxsIiCjOv hZmZ0aWePatnh5xvFD0NpP2t04cCjzjogfoPgaB7b/zbzuXU+b42kSGgn127JVH1V7JAb/76gIH Nld2O8OYAQCfWAYjEY+lcuk= X-Received: by 2002:a05:6000:4541:b0:48c:7161:43e3 with SMTP id ffacd0b85a97d-48dbacfa612mr9950364f8f.54.1791806405951; Mon, 12 Oct 2026 05:00:05 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-95-235-252-189.retail.telecomitalia.it. [95.235.252.189]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48db94e33d2sm20234313f8f.9.2026.10.12.05.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2026 05:00:05 -0700 (PDT) From: Christian Marangi To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v9 3/3] clk: en7523: add support for Airoha AN7583 clock Date: Mon, 12 Oct 2026 13:59:53 +0200 Message-ID: <20261012115954.92718-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261012115954.92718-1-ansuelsmth@gmail.com> References: <20261012115954.92718-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add support for Airoha AN7583 clock and reset. Airoha AN7583 SoC have the same register address of EN7581 but implement different bits and additional base clocks. Also reset are different with the introduction of 2 dedicated MDIO line and drop of some reset lines. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 249 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 249 insertions(+) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index ec66a504d4c5..92c88f140798 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -166,6 +167,14 @@ static const u32 crypto_base[] = { 540000000, 480000000 }; static const u32 emmc7581_base[] = { 200000000, 150000000 }; /* EN751221 */ static const u32 gsw751221_base[] = { 500000000, 250000000, 400000000, 200000000 }; +/* AN7583 */ +static const u32 gsw7583_base[] = { 540672000, 270336000, 400000000, 200000000 }; +static const u32 emi7583_base[] = { 540672000, 480000000, 400000000, 300000000 }; +static const u32 bus7583_base[] = { 600000000, 540672000, 480000000, 400000000 }; +static const u32 spi7583_base[] = { 400000000, 12500000 }; +static const u32 npu7583_base[] = { 666000000, 800000000, 720000000, 600000000 }; +static const u32 crypto7583_base[] = { 540672000, 400000000 }; +static const u32 emmc7583_base[] = { 150000000, 200000000 }; static const struct en_clk_desc en7523_base_clks[] = { { @@ -368,6 +377,138 @@ static const struct en_clk_desc en7581_base_clks[] = { } }; +static const struct en_clk_desc an7583_base_clks[] = { + { + .id = EN7523_CLK_GSW, + .name = "gsw", + + .base_reg = REG_GSW_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = gsw7583_base, + .n_base_values = ARRAY_SIZE(gsw7583_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, { + .id = EN7523_CLK_EMI, + .name = "emi", + + .base_reg = REG_EMI_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = emi7583_base, + .n_base_values = ARRAY_SIZE(emi7583_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, { + .id = EN7523_CLK_BUS, + .name = "bus", + + .base_reg = REG_BUS_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = bus7583_base, + .n_base_values = ARRAY_SIZE(bus7583_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, { + .id = EN7523_CLK_SLIC, + .name = "slic", + + .base_reg = REG_SPI_CLK_FREQ_SEL, + .base_bits = 1, + .base_shift = 1, + .base_values = slic_base, + .n_base_values = ARRAY_SIZE(slic_base), + + .div_reg = REG_SPI_CLK_DIV_SEL, + .div_bits = 5, + .div_shift = 24, + .div_val0 = 20, + .div_step = 2, + }, { + .id = EN7523_CLK_SPI, + .name = "spi", + + .base_reg = REG_SPI_CLK_FREQ_SEL, + .base_bits = 1, + .base_shift = 0, + .base_values = spi7583_base, + .n_base_values = ARRAY_SIZE(spi7583_base), + + .div_reg = REG_SPI_CLK_DIV_SEL, + .div_bits = 5, + .div_shift = 8, + .div_val0 = 40, + .div_step = 2, + }, { + .id = EN7523_CLK_NPU, + .name = "npu", + + .base_reg = REG_NPU_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 9, + .base_values = npu7583_base, + .n_base_values = ARRAY_SIZE(npu7583_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, { + .id = EN7523_CLK_CRYPTO, + .name = "crypto", + + .base_reg = REG_CRYPTO_CLKSRC2, + .base_bits = 1, + .base_shift = 0, + .base_values = crypto7583_base, + .n_base_values = ARRAY_SIZE(crypto7583_base), + }, { + .id = EN7581_CLK_EMMC, + .name = "emmc", + + .base_reg = REG_CRYPTO_CLKSRC2, + .base_bits = 1, + .base_shift = 13, + .base_values = emmc7583_base, + .n_base_values = ARRAY_SIZE(emmc7583_base), + }, { + .id = AN7583_CLK_MDIO0, + .name = "mdio0", + + .base_reg = REG_CRYPTO_CLKSRC2, + + .base_value = 25000000, + + .div_bits = 4, + .div_shift = 15, + .div_step = 1, + .div_offset = 1, + }, { + .id = AN7583_CLK_MDIO1, + .name = "mdio1", + + .base_reg = REG_CRYPTO_CLKSRC2, + + .base_value = 25000000, + + .div_bits = 4, + .div_shift = 19, + .div_step = 1, + .div_offset = 1, + } +}; + static const u16 en7581_rst_ofs[] = { REG_RST_CTRL2, REG_RST_CTRL1, @@ -543,6 +684,64 @@ static const u16 en751221_rst_map[] = { [EN751221_USB_PHY_P1_RST] = 3 * RST_NR_PER_BANK + 7, }; +static const u16 an7583_rst_map[] = { + /* RST_CTRL2 */ + [AN7583_XPON_PHY_RST] = 0, + [AN7583_GPON_OLT_RST] = 1, + [AN7583_CPU_TIMER2_RST] = 2, + [AN7583_HSUART_RST] = 3, + [AN7583_UART4_RST] = 4, + [AN7583_UART5_RST] = 5, + [AN7583_I2C2_RST] = 6, + [AN7583_XSI_MAC_RST] = 7, + [AN7583_XSI_PHY_RST] = 8, + [AN7583_NPU_RST] = 9, + [AN7583_TRNG_MSTART_RST] = 12, + [AN7583_DUAL_HSI0_RST] = 13, + [AN7583_DUAL_HSI1_RST] = 14, + [AN7583_DUAL_HSI0_MAC_RST] = 16, + [AN7583_DUAL_HSI1_MAC_RST] = 17, + [AN7583_XPON_XFI_RST] = 18, + [AN7583_WDMA_RST] = 19, + [AN7583_WOE0_RST] = 20, + [AN7583_HSDMA_RST] = 22, + [AN7583_TDMA_RST] = 24, + [AN7583_EMMC_RST] = 25, + [AN7583_SOE_RST] = 26, + [AN7583_XFP_MAC_RST] = 28, + [AN7583_MDIO0_RST] = 30, + [AN7583_MDIO1_RST] = 31, + /* RST_CTRL1 */ + [AN7583_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, + [AN7583_FE_PDMA_RST] = RST_NR_PER_BANK + 1, + [AN7583_FE_QDMA_RST] = RST_NR_PER_BANK + 2, + [AN7583_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4, + [AN7583_CRYPTO_RST] = RST_NR_PER_BANK + 6, + [AN7583_TIMER_RST] = RST_NR_PER_BANK + 8, + [AN7583_PCM1_RST] = RST_NR_PER_BANK + 11, + [AN7583_UART_RST] = RST_NR_PER_BANK + 12, + [AN7583_GPIO_RST] = RST_NR_PER_BANK + 13, + [AN7583_GDMA_RST] = RST_NR_PER_BANK + 14, + [AN7583_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, + [AN7583_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, + [AN7583_SFC_RST] = RST_NR_PER_BANK + 18, + [AN7583_UART2_RST] = RST_NR_PER_BANK + 19, + [AN7583_GDMP_RST] = RST_NR_PER_BANK + 20, + [AN7583_FE_RST] = RST_NR_PER_BANK + 21, + [AN7583_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, + [AN7583_GSW_RST] = RST_NR_PER_BANK + 23, + [AN7583_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, + [AN7583_PCIE0_RST] = RST_NR_PER_BANK + 26, + [AN7583_PCIE1_RST] = RST_NR_PER_BANK + 27, + [AN7583_CPU_TIMER_RST] = RST_NR_PER_BANK + 28, + [AN7583_PCIE_HB_RST] = RST_NR_PER_BANK + 29, + [AN7583_XPON_MAC_RST] = RST_NR_PER_BANK + 31, + + /* RST_PCIC */ + [AN7583_PCIC_PERSTOUT0_RST] = 2 * RST_NR_PER_BANK + 29, + [AN7583_PCIC_PERSTOUT1_RST] = 2 * RST_NR_PER_BANK + 26, +}; + static int en7581_reset_register(struct device *dev, void __iomem *base, const u16 *rst_map, int nr_resets, const u16 *rst_reg_ofs); @@ -1088,6 +1287,43 @@ static int en7581_clk_hw_init(struct platform_device *pdev, return en7581_serdes_phy_register(&pdev->dev); } +static int an7583_clk_hw_init(struct platform_device *pdev, + struct clk_hw_onecell_data *clk_data) +{ + struct en_clk_priv *priv = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + struct regmap *map; + void __iomem *base; + u32 val; + int ret; + + map = syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,chip-scu"); + if (IS_ERR(map)) + return PTR_ERR(map); + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->base = base; + + en7581_register_clocks(dev, clk_data, map, base); + + val = readl(base + REG_RST_CTRL1); + val |= REG_PCIE_HB_RST; + writel(val, base + REG_RST_CTRL1); + val &= ~REG_PCIE_HB_RST; + writel(val, base + REG_RST_CTRL1); + + ret = en7581_reset_register(dev, base, an7583_rst_map, + ARRAY_SIZE(an7583_rst_map), + en7581_rst_ofs); + if (ret) + return ret; + + return en7581_serdes_phy_register(dev); +} + static enum en_hir get_hw_id(void __iomem *np_base) { u32 val = FIELD_GET(REG_HIR_MASK, readl(np_base + REG_HIR)); @@ -1241,6 +1477,18 @@ static const struct en_clk_soc_data en7581_data = { .hw_init = en7581_clk_hw_init, }; +static const struct en_clk_soc_data an7583_data = { + .base_clks = an7583_base_clks, + /* We increment num_clocks by 1 to account for additional PCIe clock */ + .num_clocks = ARRAY_SIZE(an7583_base_clks) + 1, + .pcie_ops = { + .is_enabled = en7581_pci_is_enabled, + .enable = en7581_pci_enable, + .disable = en7581_pci_disable, + }, + .hw_init = an7583_clk_hw_init, +}; + static const struct en_clk_soc_data en751221_data = { .num_clocks = EN751221_MAX_CLKS, .pcie_ops = { @@ -1254,6 +1502,7 @@ static const struct en_clk_soc_data en751221_data = { static const struct of_device_id of_match_clk_en7523[] = { { .compatible = "airoha,en7523-scu", .data = &en7523_data }, { .compatible = "airoha,en7581-scu", .data = &en7581_data }, + { .compatible = "airoha,an7583-scu", .data = &an7583_data }, { .compatible = "econet,en751221-scu", .data = &en751221_data }, { /* sentinel */ } }; -- 2.55.0