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Mon, 12 Oct 2026 08:24:16 -0700 (PDT) From: Alex Elder To: sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org Cc: abelvesa@kernel.org, kees@kernel.org, gustavoars@kernel.org, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, danielt@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Thompson Subject: [PATCH v3 3/4] arm64: dts: qcom: define a fixed 25 MHz clock Date: Mon, 12 Oct 2026 10:24:06 -0500 Message-ID: <20261012152408.3729237-4-elder@riscstar.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261012152408.3729237-1-elder@riscstar.com> References: <20261012152408.3729237-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The TC9564 SoC has a single 25 MHz fixed-rate input clock. Add it to the definition associated with the chip. Co-developed-by: Daniel Thompson Signed-off-by: Daniel Thompson Signed-off-by: Alex Elder --- v3: - New patch in this version of the series arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 0e3bbdaf4661f..b8d290eed2f38 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -891,6 +891,12 @@ pcie@0,0 { pinctrl-0 = <&tc9563_resx_n>; pinctrl-names = "default"; + clock-25000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + pcie1_switch0_dsp1: pcie@1,0 { reg = <0x20800 0x0 0x0 0x0 0x0>; #address-cells = <3>; -- 2.53.0