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From: Ali Rouhi <arouhi@sitime.com>
To: "ivecera@redhat.com" <ivecera@redhat.com>
Cc: Jiri Pirko <jiri@resnulli.us>,
	Vadim Fedorenko <vadim.fedorenko@linux.dev>,
	Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Carolina Jubran <cjubran@nvidia.com>,
	Oleg Zadorozhnyi <Oleg.Zadorozhnyi@devoxsoftware.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH net-next v12 08/12] dpll: sit9531x: add support to get and set frequency on pins
Date: Tue, 13 Oct 2026 22:36:43 +0000	[thread overview]
Message-ID: <20261013223641.25560-2-arouhi@sitime.com> (raw)
In-Reply-To: <0051c3dd-6abd-4ff1-a125-7cace9fac6fb@redhat.com>

On Tue, 13 Oct 2026, Ivan Vecera wrote:

> > +       /*
> > +        * An output's current rate is the one its divider produces, so read
> > +        * it rather than assume the first entry of a list of the rates the
> > +        * board supports is the one in force.  A rate taken from firmware
> > +        * that the part is not running would be reported as current and,
> > +        * worse, used as the output period the phase adjust quantizes
> > +        * against.  An output the configuration does not route has no rate
> > +        * to read, which is not an error.
> > +        */
> > +       if (dir == DPLL_PIN_DIRECTION_OUTPUT &&
> > +           index < sitdev->info->num_outputs) {
> > +               u64 hw_freq;
> > +
> > +               mutex_lock(&sitdev->multiop_lock);
> > +               rc = sit9531x_output_freq_get(sitdev, index, &hw_freq);
> > +               mutex_unlock(&sitdev->multiop_lock);
> > +               if (!rc)
> > +                       curr_freq = hw_freq;
> > +       }
> > +
> >   skip_fwnode_props:
>
> This read-back sits before the skip_fwnode_props label, so an output with
> no firmware node, or with a node that has no supported-frequencies-hz.
>
> For such an output curr_freq stays at the zero-initialized
> sitdev->out[index].freq, so the current rate is neither cached nor listed
> ahead of the 1 Hz to 1 GHz fallback range.  Was the read-back meant to
> cover outputs without a firmware frequency list as well?

Yes, it was meant for every output. An output the board describes
without a rate list, or does not describe at all, still runs at
whatever its divider produces, and that is the rate to publish. Sitting
before the label it was skipped for exactly those outputs.

In v13 the read-back sits past the label, so each output publishes the
rate its divider produces ahead of the fallback range. The two INTSYNC
early returns move above it, since neither of those pins carries a
frequency attribute and neither has a divider to read. The comment
above the read-back says this rather than the old sentence about a
routed output, which was describing the restriction rather than the
intent.

Thanks,
Ali

  reply	other threads:[~2026-10-13 22:36 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-09 18:31 [PATCH net-next v12 00/12] dpll: add SiTime SiT9531x DPLL clock driver Ali Rouhi
2026-10-09 18:31 ` [PATCH net-next v12 01/12] dt-bindings: vendor-prefixes: add SiTime Corporation Ali Rouhi
2026-10-09 18:31 ` [PATCH net-next v12 02/12] dt-bindings: dpll: add SiTime SiT95316 clock generator Ali Rouhi
2026-10-09 18:31 ` [PATCH net-next v12 03/12] dpll: add basic SiTime SiT9531x support Ali Rouhi
2026-10-10 18:32   ` sashiko-bot
2026-10-13  9:11   ` Ivan Vecera
2026-10-13 22:36     ` Ali Rouhi
2026-10-09 18:31 ` [PATCH net-next v12 05/12] dpll: sit9531x: register DPLL devices and pins Ali Rouhi
2026-10-10 18:32   ` sashiko-bot
2026-10-13  9:35   ` Ivan Vecera
2026-10-09 18:31 ` [PATCH net-next v12 04/12] dpll: sit9531x: read DPLL types and pin properties from system firmware Ali Rouhi
2026-10-13  9:14   ` Ivan Vecera
2026-10-09 18:31 ` [PATCH net-next v12 06/12] dpll: sit9531x: implement input pin state on a DPLL Ali Rouhi
2026-10-13  9:37   ` Ivan Vecera
2026-10-09 18:31 ` [PATCH net-next v12 08/12] dpll: sit9531x: add support to get and set frequency on pins Ali Rouhi
2026-10-10 18:32   ` sashiko-bot
2026-10-13  9:43   ` Ivan Vecera
2026-10-13 22:36     ` Ali Rouhi [this message]
2026-10-09 18:31 ` [PATCH net-next v12 07/12] dpll: sit9531x: add support to get and set priority on input pins Ali Rouhi
2026-10-13  9:43   ` Ivan Vecera
2026-10-09 18:31 ` [PATCH net-next v12 09/12] dpll: sit9531x: implement output pin state on a DPLL Ali Rouhi
2026-10-13  9:46   ` Ivan Vecera
2026-10-13 22:36     ` Ali Rouhi
2026-10-09 18:31 ` [PATCH net-next v12 10/12] dpll: sit9531x: add support to adjust output phase Ali Rouhi
2026-10-13 10:02   ` Ivan Vecera
2026-10-13 22:36     ` Ali Rouhi
2026-10-09 18:31 ` [PATCH net-next v12 11/12] dpll: sit9531x: add support to get phase offset on the connected input pin Ali Rouhi
2026-10-13 10:10   ` Ivan Vecera
2026-10-09 18:32 ` [PATCH net-next v12 12/12] dpll: sit9531x: model the inter-PLL sync net as a pair of pins Ali Rouhi

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