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Switch shikra_cfg to the new table so other platforms with the same block can reuse it. Add lcp_irq to struct llcc_drv_data and retrieve the optional second interrupt in qcom_llcc_probe(), propagating non-absence errors so the driver defers correctly. Signed-off-by: Faiyaz Mohammed --- drivers/soc/qcom/llcc-qcom.c | 45 ++++++++++++++++++++++++++++++++++++-- include/linux/soc/qcom/llcc-qcom.h | 13 +++++++++++ 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index d7a42a8040a1..39e0da14b36d 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -4509,6 +4509,41 @@ static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = { .drp_ecc_db_err_syn0 = 0x52120, }; +static const struct llcc_edac_reg_offset llcc_lcp_srp_edac_reg_offset = { + .trp_ecc_error_status0 = 0x20344, + .trp_ecc_error_status1 = 0x20348, + .trp_ecc_sb_err_syn0 = 0x2034c, + .trp_ecc_db_err_syn0 = 0x20370, + .trp_ecc_error_cntr_clear = 0x20440, + .trp_interrupt_0_status = 0x20480, + .trp_interrupt_0_clear = 0x20484, + .trp_interrupt_0_enable = 0x20488, + + /* LLCC Common registers */ + .cmn_status0 = 0x3400c, + .cmn_interrupt_0_enable = 0x3401c, + .cmn_interrupt_1_enable = 0x3402c, + .cmn_interrupt_2_enable = 0x3403c, + + /* LLCC DRP registers */ + .drp_ecc_error_cfg = 0x50000, + .drp_ecc_error_cntr_clear = 0x50004, + .drp_interrupt_status = 0x50020, + .drp_interrupt_clear = 0x50028, + .drp_interrupt_enable = 0x5002c, + .drp_ecc_error_status0 = 0x520f4, + .drp_ecc_error_status1 = 0x520f8, + .drp_ecc_sb_err_syn0 = 0x520fc, + .drp_ecc_db_err_syn0 = 0x52120, + + /* LCP/SRP DDR DRAM ECC registers */ + .lcp_srp_ecc_error_cntr_clear = 0x59004, + .lcp_srp_ecc_error_status1 = 0x59010, + .lcp_srp_interrupt_status = 0x59070, + .lcp_srp_interrupt_clear = 0x59074, + .lcp_srp_interrupt_enable = 0x59078, +}; + static const struct llcc_edac_reg_offset llcc_v6_edac_reg_offset = { .trp_ecc_error_status0 = 0x47448, .trp_ecc_error_status1 = 0x47450, @@ -4767,7 +4802,7 @@ static const struct qcom_llcc_config shikra_cfg[] = { .sct_data = shikra_data, .size = ARRAY_SIZE(shikra_data), .reg_offset = llcc_v2_1_reg_offset, - .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + .edac_reg_offset = &llcc_lcp_srp_edac_reg_offset, .irq_configured = true, }, }; @@ -5798,7 +5833,13 @@ static int qcom_llcc_probe(struct platform_device *pdev) if (drv_data->ecc_irq < 0 && drv_data->ecc_irq != -ENXIO) return dev_err_probe(&pdev->dev, drv_data->ecc_irq, "failed to get IRQ resource\n"); - + if (cfg->edac_reg_offset && cfg->edac_reg_offset->lcp_srp_interrupt_enable) { + drv_data->lcp_irq = platform_get_irq_optional(pdev, 1); + if (drv_data->lcp_irq < 0 && drv_data->lcp_irq != -ENXIO) { + ret = drv_data->lcp_irq; + goto err; + } + } drv_data->edac_reg_offset = cfg->edac_reg_offset; drv_data->ecc_irq_configured = cfg->irq_configured; drv_data->dev = dev; diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 713cb0221b14..020d0b4116d2 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -139,6 +139,7 @@ struct llcc_edac_reg_offset { /* LLCC Common registers */ u32 cmn_status0; u32 cmn_interrupt_0_enable; + u32 cmn_interrupt_1_enable; u32 cmn_interrupt_2_enable; /* LLCC DRP registers */ @@ -151,6 +152,16 @@ struct llcc_edac_reg_offset { u32 drp_ecc_error_status1; u32 drp_ecc_sb_err_syn0; u32 drp_ecc_db_err_syn0; + + /* + * LCP/SRP DDR DRAM ECC registers (LLCC broadcast space). + * Zero on platforms that do not support LCP/SRP ECC reporting. + */ + u32 lcp_srp_ecc_error_cntr_clear; + u32 lcp_srp_ecc_error_status1; + u32 lcp_srp_interrupt_status; + u32 lcp_srp_interrupt_clear; + u32 lcp_srp_interrupt_enable; }; /** @@ -165,6 +176,7 @@ struct llcc_edac_reg_offset { * @cfg_size: size of the config data table * @num_banks: Number of LLCC banks * @ecc_irq: interrupt for LLCC cache error detection and reporting + * @lcp_irq: interrupt for LCP/SRP DDR DRAM ECC error reporting or negative errno on failure * @ecc_irq_configured: 'True' if firmware has already configured the irq propagation * @version: Indicates the LLCC version * @desc: Array pointer of pre-allocated LLCC slice descriptors @@ -180,6 +192,7 @@ struct llcc_drv_data { u32 cfg_size; u32 num_banks; int ecc_irq; + int lcp_irq; bool ecc_irq_configured; u32 version; struct llcc_slice_desc *desc; -- 2.34.1