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Wed, 14 Oct 2026 08:56:49 -0700 (PDT) X-Received: by 2002:a17:903:1247:b0:2e8:c331:fc30 with SMTP id d9443c01a7336-2e8c33202e1mr77158925ad.69.1791993408736; Wed, 14 Oct 2026 08:56:48 -0700 (PDT) Received: from hu-faiyazm-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e8422e14f6sm71961375ad.69.2026.10.14.08.56.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2026 08:56:48 -0700 (PDT) From: Faiyaz Mohammed Date: Wed, 14 Oct 2026 21:26:18 +0530 Subject: [PATCH 3/4] edac: qcom: add LCP/SRP DDR DRAM ECC support for Shikra Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261014-master-v1-3-aba3cfcfbac9@oss.qualcomm.com> References: <20261014-master-v1-0-aba3cfcfbac9@oss.qualcomm.com> In-Reply-To: <20261014-master-v1-0-aba3cfcfbac9@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam , Borislav Petkov , Tony Luck , Conor Dooley , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, Faiyaz Mohammed X-Mailer: b4 0.15.2 X-Authority-Analysis: v=2.4 cv=PYJqFShd c=1 sm=1 tr=0 ts=6acfa642 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=Ij1zGpOROYN2N0QOU-8A:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE0MDA2MyBTYWx0ZWRfXwTDmL436C2J6 wX1F7nN6sV5x5GUcnrEIZHD+Rq5Ej8oFfenPwxNl0GoCqKUFoPC8BEvNtUww3haSB93hIBVoUFa gqbapIpYL/G6IPjeGWTLr3qtxUkM9/Q= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE0MDA2MyBTYWx0ZWRfX3XsvnMdM3z+P cOtw/tMwzeLCGj48YflAjrE9tlpX9Hk53sYL0CJw7TdbeVzvXbrjQ6R8wX4M+0Bf6GdsNo1PGTV mmCzvkjYci/saQ6fDpfPpc+UpnbjxroPJYHamHrUb9qo8JsK8NnETKPtHDt3O4SPDfZT6fgB/Y3 3UStE4AsR84ieDwRiDe3PpFArEKXena9hr/s9Ezcjb8MrB3K8dOicYM91PE72e3ks1Ioseev6tB Nv/OPWaVqWXICKjb5A7gbn7mMWs7FrVL3HmUBa1uHWoIxmjWMrJNqMwpqJ3xXkgy2GGAnScWxby dGTRFj9EIfVqQFH47RasUcMFINpz9F5OCI2FLrgS89I5dJt8BLS09wjEXg1fJFRz9AEQTJEvvYx EeZu79lIBvrv35B1VszucFdDNSO9wLRj+iojsnqzMDB/R2bKmkaCIuH29MJUIg8nnljOH1QTSsP tqFUaqx1ei7kgYIUN0Q== X-Proofpoint-GUID: 6vKK64s18C2u7c1b2b_q0gedQfhOaCRD X-Proofpoint-ORIG-GUID: 6vKK64s18C2u7c1b2b_q0gedQfhOaCRD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610140063 Add qcom_llcc_lcp_setup() to enable LCP/SRP interrupt routing when firmware has not pre-configured it, and llcc_lcp_ecc_irq_handler() to report per-bank correctable and uncorrectable DDR DRAM ECC errors. LCP/SRP setup is skipped when ecc_irq_configured is set (e.g. Shikra, where DSF firmware handles IRQ routing). A missing lcp_irq is non-fatal; TRP/DRP ECC reporting continues unaffected. Signed-off-by: Faiyaz Mohammed --- drivers/edac/qcom_edac.c | 147 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index f3da9385ca0d..b4f7b2493650 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -3,6 +3,7 @@ * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -44,8 +45,16 @@ #define SB_DB_TRP_INTERRUPT_ENABLE 0x3 #define TRP0_INTERRUPT_ENABLE 0x1 #define DRP0_INTERRUPT_ENABLE BIT(6) +#define SRP_INTERRUPT_ENABLE BIT(7) #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 +/* LCP/SRP DDR DRAM ECC */ +#define LCP_SB_ECC_ERROR BIT(0) +#define LCP_DB_ECC_ERROR BIT(1) +#define LCP_SRP_SB_DB_INTERRUPT_ENABLE 0x3 +#define LCP_DB_ERR_COUNT_MASK GENMASK(4, 0) +#define LCP_SB_ERR_COUNT_MASK GENMASK(23, 16) + #define ECC_POLL_MSEC 5000 enum { @@ -124,6 +133,29 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b return ret; } +/* + * Enable LCP/SRP DDR DRAM ECC interrupt generation and route events to + * ddrss_apps_interrupt[1] via cmn_interrupt_1_enable. Only called when + * !ecc_irq_configured; on platforms like Shikra where firmware pre-configures + * both TRP/DRP and LCP/SRP routing, the driver skips this and only requests + * the IRQ handler. + */ +static int qcom_llcc_lcp_setup(struct llcc_drv_data *drv, + struct regmap *llcc_bcast_regmap) +{ + int ret; + + ret = regmap_set_bits(llcc_bcast_regmap, + drv->edac_reg_offset->cmn_interrupt_1_enable, + SRP_INTERRUPT_ENABLE); + if (ret) + return ret; + + return regmap_set_bits(llcc_bcast_regmap, + drv->edac_reg_offset->lcp_srp_interrupt_enable, + LCP_SRP_SB_DB_INTERRUPT_ENABLE); +} + /* Clear the error interrupt and counter registers */ static int qcom_llcc_clear_error_status(int err_type, struct llcc_drv_data *drv) @@ -334,6 +366,92 @@ static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl) llcc_ecc_irq_handler(0, edev_ctl); } +/* + * Handler for the optional LCP/SRP DDR DRAM ECC interrupt + * (ddrss_apps_interrupt[1]). The LCP/SRP registers live in each LLCC + * instance's address space, so iterate over all banks and read status + * per-instance. Broadcast-write the clear after the full loop, mirroring + * the TRP/DRP handler pattern. + */ +static irqreturn_t llcc_lcp_ecc_irq_handler(int irq, void *edev_ctl) +{ + struct edac_device_ctl_info *edac_dev_ctl = edev_ctl; + struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data; + const struct llcc_edac_reg_offset *reg = drv->edac_reg_offset; + irqreturn_t irq_rc = IRQ_NONE; + u32 intr_status, err_status, clr_reg; + int i, ret; + + /* Iterate over banks: LCP/SRP status registers are per-LLCC instance */ + for (i = 0; i < drv->num_banks; i++) { + ret = regmap_read(drv->regmaps[i], reg->lcp_srp_interrupt_status, + &intr_status); + if (ret) + continue; + + intr_status &= LCP_SB_ECC_ERROR | LCP_DB_ECC_ERROR; + if (!intr_status) + continue; + + irq_rc = IRQ_HANDLED; + + ret = regmap_read(drv->regmaps[i], reg->lcp_srp_ecc_error_status1, + &err_status); + if (ret) { + edac_printk(KERN_ERR, EDAC_LLCC, + "LCP/SRP error status read failed for bank%u: %d\n", + i, ret); + continue; + } + + if (intr_status & LCP_DB_ECC_ERROR) { + u32 db_cnt = FIELD_GET(LCP_DB_ERR_COUNT_MASK, err_status); + + edac_printk(KERN_CRIT, EDAC_LLCC, + "LCP/SRP DDR DRAM Double-bit ECC error in bank%u: count=%u status=0x%08x\n", + i, db_cnt, err_status); + edac_device_handle_ue(edac_dev_ctl, 0, i, + "LCP/SRP DDR DRAM uncorrectable error"); + } + + if (intr_status & LCP_SB_ECC_ERROR) { + u32 sb_cnt = FIELD_GET(LCP_SB_ERR_COUNT_MASK, err_status); + + edac_printk(KERN_WARNING, EDAC_LLCC, + "LCP/SRP DDR DRAM Single-bit ECC error in bank%u: count=%u status=0x%08x\n", + i, sb_cnt, err_status); + edac_device_handle_ce(edac_dev_ctl, 0, i, + "LCP/SRP DDR DRAM correctable error"); + } + } + + if (irq_rc != IRQ_HANDLED) + return irq_rc; + + clr_reg = reg->lcp_srp_interrupt_clear ? + reg->lcp_srp_interrupt_clear : + reg->lcp_srp_interrupt_status; + + if (clr_reg) { + ret = regmap_write(drv->bcast_regmap, clr_reg, + LCP_SB_ECC_ERROR | LCP_DB_ECC_ERROR); + if (ret) + edac_printk(KERN_ERR, EDAC_LLCC, + "LCP/SRP interrupt clear failed: %d\n", ret); + } + + if (reg->lcp_srp_ecc_error_cntr_clear) { + ret = regmap_write(drv->bcast_regmap, + reg->lcp_srp_ecc_error_cntr_clear, + DRP_TRP_CNT_CLEAR); + if (ret) + edac_printk(KERN_ERR, EDAC_LLCC, + "LCP/SRP counter clear failed: %d\n", ret); + } + + return irq_rc; +} + static int qcom_llcc_edac_probe(struct platform_device *pdev) { struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data; @@ -372,6 +490,8 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) edac_op_state = EDAC_OPSTATE_INT; goto irq_done; } + dev_warn(dev, "failed to request LLCC ECC irq %d: %d, falling back to polling\n", + ecc_irq, rc); } /* Fall back to polling mode otherwise */ @@ -386,6 +506,33 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) return rc; } + /* + * Set up LCP/SRP DDR DRAM ECC after the EDAC device is published. + * Skip hardware routing setup if firmware already configured IRQ + * propagation (irq_configured); only request the IRQ handler. + * Guard on a non-zero lcp_srp_interrupt_enable offset to confirm + * this LLCC variant actually has an LCP/SRP block. + */ + if (llcc_driv_data->lcp_irq > 0 && + llcc_driv_data->edac_reg_offset->lcp_srp_interrupt_enable) { + if (!llcc_driv_data->ecc_irq_configured) { + rc = qcom_llcc_lcp_setup(llcc_driv_data, + llcc_driv_data->bcast_regmap); + if (rc) { + dev_warn(dev, "LCP/SRP interrupt setup failed: %d\n", rc); + goto lcp_done; + } + } + rc = devm_request_irq(dev, llcc_driv_data->lcp_irq, + llcc_lcp_ecc_irq_handler, + 0, "llcc_lcp_ecc", edev_ctl); + if (rc) + dev_warn(dev, + "failed to request LCP ECC irq %d: %d, DDR DRAM ECC reporting disabled\n", + llcc_driv_data->lcp_irq, rc); + } +lcp_done: + rc = 0; platform_set_drvdata(pdev, edev_ctl); return rc; -- 2.34.1