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Wed, 14 Oct 2026 16:34:24 -0500 From: Ben Levinsky To: , , , , , CC: , , , , , , Subject: [PATCH 3/6] dt-bindings: mailbox: Add AMD PL Mailbox IP Date: Wed, 14 Oct 2026 14:34:23 -0700 Message-ID: <20261014213426.2957480-4-ben.levinsky@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261014213426.2957480-1-ben.levinsky@amd.com> References: <20261014213426.2957480-1-ben.levinsky@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C5:EE_|SA3PR12MB176418:EE_ X-MS-Office365-Filtering-Correlation-Id: 51372076-bd34-4360-ab3c-08df2a3af0c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|23010399003|36860700016|1800799024|376014|7416014|10067099003|18002099003|22082099003|3023799007|13003099007|11063799006|261009223027099003|56012099006; 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The same IP is used on ZynqMP, Versal, Versal NET and Versal Gen 2. Name each SoC in its compatible, and use amd,zynqmp-pl-mbox-2.1 as the fallback that drivers match. Define the transmit and receive channel indices together with the register aperture, interrupt, and interface clock. Describe the FIFO depth chosen when the IP is configured, so that the driver can size received messages to it. Assisted-by: LLM sparse Signed-off-by: Ben Levinsky --- .../mailbox/amd,zynqmp-pl-mbox-2.1.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl-mbox-2.1.yaml diff --git a/Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl-mbox-2.1.yaml b/Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl-mbox-2.1.yaml new file mode 100644 index 000000000000..2cc0d106b888 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl-mbox-2.1.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/amd,zynqmp-pl-mbox-2.1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Programmable Logic Mailbox IP + +maintainers: + - Ben Levinsky + +description: | + The AMD Programmable Logic Mailbox IP provides bidirectional message passing + between two processor-facing interfaces. Each interface writes messages to + a send FIFO and reads messages from a receive FIFO. The register aperture, + interrupt, and clock described by a node belong to one processor-facing + interface. Channel 0 represents transmit and channel 1 represents receive + for that interface. + +properties: + compatible: + oneOf: + - const: amd,zynqmp-pl-mbox-2.1 + - items: + - enum: + - amd,versal-pl-mbox-2.1 + - amd,versal-net-pl-mbox-2.1 + - amd,versal2-pl-mbox-2.1 + - const: amd,zynqmp-pl-mbox-2.1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + amd,mbox-pl-fifo-len: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 16 + maximum: 8192 + default: 16 + description: + Depth of the send and receive FIFOs in 32-bit words, as configured by + the C_MAILBOX_DEPTH parameter of the IP. Must match the configured + depth. + + '#mbox-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + #include + + mailbox@b2060000 { + compatible = "amd,zynqmp-pl-mbox-2.1"; + reg = <0xb2060000 0x10000>; + interrupts = ; + clocks = <&pl_clk>; + amd,mbox-pl-fifo-len = <16>; + #mbox-cells = <1>; + }; +... -- 2.34.1