From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ACC53C1D42; Thu, 15 Oct 2026 14:54:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792076042; cv=none; b=jESYTiaWplcN9PTVww8/9NglahsVebmz7fLzL19PkGYiBgTViv0/xyeJoB1gnqCVxd+rnu0lbcORAbsduKgltpVVF+EeMM25W7W54ABcmBa4GUl2ZuHNCTtu5yoAthN5WhxvWlWuZKN+QQg7fRfCHw3uk9QdEhO6B7h+guBfRN4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792076042; c=relaxed/simple; bh=Ze4Nv8y680E6FSf/un9hYJUthpJ2COzdxd+LB34Yb2I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=a1emQbI7mFXSb7Wwgi4sZz0/EGrZOpFV7HGvWJh/JYDTFwqb9urgtjoErrvpQ/IfOPoDwfTUIIy2Qt42wVtssESKuSPTjQplNiNaE7yZT6gk8PFONP6vqZp60QP6w02gfGpzWJ82N+22PzVUq5B8UP7qvjU3yxsye2JIm1tE1B4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=Eac5jeWQ; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="Eac5jeWQ" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 257165AF213; Thu, 15 Oct 2026 16:53:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1792076037; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=X5WYmjC+W1XLRGqsI2xwQZ9HsjRo/iUHSgzYnXKRgcw=; b=Eac5jeWQ5zpCryMAVqi4ZUd2etg9UZzTxGyQKWRSXvBuiUe5M1M+XVjIs0qjmJ0ZBj/Qnk 5x1G+BcS0lb8GkacCYAhxG2kZzr+FY3A2bpRbTtjE+w9QSceWHxWX6ke8td856C6gjVBZM 6QsiR6hsVZvSh9cxcL/8b0PhY8JDRdJo8HAsiaqia6L+KQMMYv9I2oRb86hOTuQUFOIthT wG+BM8eKRP7bnM4GpZXC+M46g7WkWIg+5eLaCMx8Wb7IZX2mkzdERiaWKtKOp5OkGBZ+vK Y+TrHkjSzR7j31++8Dw+pJgQNOE5nKzx+ah3mvNQAsK0+plkgkohokxA4knfnw== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, grandmaster@al2klimov.de, Caleb James DeLisle , Conor Dooley Subject: [PATCH v10 1/5] dt-bindings: timer: econet: Update EN751627 for multi-IRQ Date: Thu, 15 Oct 2026 14:53:27 +0000 Message-Id: <20261015145331.453837-2-cjd@cjdns.fr> In-Reply-To: <20261015145331.453837-1-cjd@cjdns.fr> References: <20261015145331.453837-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 This hardware is found in the EN751221 SoC family as well as the EN751627. The former uses a percpu IRQ for all timers while the latter uses an individual IRQ number per timer. Signed-off-by: Caleb James DeLisle Acked-by: Conor Dooley --- .../bindings/timer/econet,en751221-timer.yaml | 31 ++++++++++++------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml index c1e7c2b6afde..ac25785ecfdf 100644 --- a/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml +++ b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml @@ -12,24 +12,23 @@ maintainers: description: The EcoNet High Precision Timer (HPT) is a timer peripheral found in various EcoNet SoCs, including the EN751221 and EN751627 families. It provides per-VPE - count/compare registers and a per-CPU control register, with a single interrupt - line using a percpu-devid interrupt mechanism. + count/compare registers and a per-CPU control register. On EN751221 it uses a + single interrupt line using a percpu-devid interrupt mechanism, and on + EN751627 it uses an interrupt per VPE. properties: compatible: - oneOf: - - const: econet,en751221-timer - - items: - - const: econet,en751627-timer - - const: econet,en751221-timer + enum: + - econet,en751221-timer + - econet,en751627-timer reg: minItems: 1 maxItems: 2 interrupts: - maxItems: 1 - description: A percpu-devid timer interrupt shared across CPUs. + minItems: 1 + maxItems: 4 clocks: maxItems: 1 @@ -52,21 +51,31 @@ allOf: items: - description: VPE timers 0 and 1 - description: VPE timers 2 and 3 + interrupts: + description: An interrupt for each timer (one per VPE) + minItems: 4 else: properties: reg: items: - description: VPE timers 0 and 1 + interrupts: + description: A percpu-devid timer interrupt shared across timers + maxItems: 1 additionalProperties: false examples: - | + #include timer@1fbf0400 { - compatible = "econet,en751627-timer", "econet,en751221-timer"; + compatible = "econet,en751627-timer"; reg = <0x1fbf0400 0x100>, <0x1fbe0000 0x100>; interrupt-parent = <&intc>; - interrupts = <30>; + interrupts = , + , + , + ; clocks = <&hpt_clock>; }; - | -- 2.39.5