From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 226535304D4; Thu, 15 Oct 2026 14:54:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792076050; cv=none; b=gL417RU2TUwYc8smeOk/ah9bbOGdAyXbZMyL9RAZCfmLFOQU1ML25GfYOyUMmA7DMgjH1Bzqm2FhdTWttashXwRbHtNb4Mpj/jZbu6JUz/AKPbU8NSEVaSKi55wHmUssH80DZPvtzuHy1KTASw5r/jG3G+RGe7wg2FzWtHK1ZXk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792076050; c=relaxed/simple; bh=560hfu6+QgnwiQwoTADYAgBHD2mtOh6a5Kfe5puvTpM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aUwOqXbpDXRLRm8mmgOtXLarrXTymoPC0adntk509NecbKIUrwbrw1K8uoHLDnGvQ/mxTFWjHhDcTKtyr9BKyG+ZYaBf4c5QVgSr+7gvQLTiowVp7CdP5Y8BIEhqtyp5hc1s5fwTf520H/O/tX/AtVhV7J+5d5gwFRCusRhX3YU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=Vk86sn5o; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="Vk86sn5o" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 936EF5AE316; Thu, 15 Oct 2026 16:54:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1792076046; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=3gfOVfkp/8piD56YZiuRHk4Yu7992KRO2z+15M4CIs8=; b=Vk86sn5o38BT29X9/z7zd3134ZFPTAwXggCUlXVjjKS+PiKgobJOeVkVKS6/iHBipziWoE NV9fL2oLOcP9wdSJNDOjNM7pw/eO1yK6cvbGdJnhZ4aMHs2evrDK0qnOaNuYxGSnofZNMr A5KFw/m94LFu1WtFZNZfQwAxiwjZxC5cIByR6KJ/SvhEegJn8nRmZPgfv6BA/G7k7KvHAH +SYNc3cFSLupi5kOYWIqVkc56Rk2c447+AT90OQOAD4L/DV6k7bhHyHIUfmrwZ5CANJQJh RFVMJyORu9kFhR6l+MvzeL/2jbEayjfhrkZTqxdbvLi1JyyhqErcDLN7zNN/zA== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, grandmaster@al2klimov.de, Caleb James DeLisle Subject: [PATCH v10 5/5] clocksource/timer-econet-en751221: Do not use NR_CPUS for resource array size Date: Thu, 15 Oct 2026 14:53:31 +0000 Message-Id: <20261015145331.453837-6-cjd@cjdns.fr> In-Reply-To: <20261015145331.453837-1-cjd@cjdns.fr> References: <20261015145331.453837-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 Each pair of VPEs has one timer block, so the number of blocks is half the number of CPUs on the hardware. However, since NR_CPUS is a configuration, it is possible that it will be less than the number of actual CPUs on the hardware which will cause the array to be too small for the specified DT. Switch to an allocated buffer for storing the iomem resources, as is done for the IRQs. Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 29 ++++++++++++++------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksource/timer-econet-en751221.c index ebcc6fa34218..739d95275385 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -19,11 +19,10 @@ #define ECONET_BITS 32 #define ECONET_MIN_DELTA 0x00001000 #define ECONET_MAX_DELTA GENMASK(ECONET_BITS - 2, 0) -/* 34Kc hardware has 1 block and 1004Kc has 2. */ -#define ECONET_NUM_BLOCKS DIV_ROUND_UP(NR_CPUS, 2) static struct { - void __iomem *membase[ECONET_NUM_BLOCKS]; + void __iomem **membase; + int num_membase; int *irqs; int num_irqs; bool is_percpu; @@ -37,6 +36,10 @@ static DEFINE_PER_CPU(struct clock_event_device, econet_timer_pcpu); */ static inline void __iomem *reg_ctl(u32 timer_n) { + /* reg_ctl() is used to check if a clock exists */ + if (timer_n >> 1 >= econet_timer.num_membase) + return NULL; + return econet_timer.membase[timer_n >> 1]; } @@ -200,11 +203,6 @@ static int __init timer_init(struct device_node *np) num_irqs); return -EINVAL; } - if (num_blocks > ARRAY_SIZE(econet_timer.membase)) { - pr_err("%pOFn: Too many regs: max %zd got %d\n", np, - ARRAY_SIZE(econet_timer.membase), num_blocks); - return -EINVAL; - } if (num_blocks == 0) { pr_err("%pOFn: At least one reg block must be provided\n", np); return -EINVAL; @@ -225,6 +223,15 @@ static int __init timer_init(struct device_node *np) if (!econet_timer.irqs) return -ENOMEM; + econet_timer.num_membase = num_blocks; + econet_timer.membase = kcalloc(num_blocks, + sizeof(*econet_timer.membase), + GFP_KERNEL); + if (!econet_timer.membase) { + ret = -ENOMEM; + goto out_kfree_irqs; + } + for (i = 0; i < num_blocks; i++) { econet_timer.membase[i] = of_iomap(np, i); if (!econet_timer.membase[i]) { @@ -303,13 +310,17 @@ static int __init timer_init(struct device_node *np) irq_dispose_mapping(econet_timer.irqs[i]); } out_membase: - for (int i = 0; i < ARRAY_SIZE(econet_timer.membase); i++) { + for (int i = 0; i < num_blocks; i++) { if (econet_timer.membase[i]) { iounmap(econet_timer.membase[i]); econet_timer.membase[i] = NULL; } } + kfree(econet_timer.membase); + econet_timer.membase = NULL; + +out_kfree_irqs: kfree(econet_timer.irqs); econet_timer.irqs = NULL; -- 2.39.5