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[211.23.39.77]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e97e882a20sm6971025ad.62.2026.10.16.01.57.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2026 01:57:15 -0700 (PDT) From: Jason Yang Date: Fri, 16 Oct 2026 16:56:41 +0800 Subject: [PATCH v5 7/8] arm64: dts: rockchip: use two phy cells for the rk3588 mipi dcphys Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261016-dcphy-rx-v1-v5-7-e63b49eabe2d@gmail.com> References: <20261016-dcphy-rx-v1-v5-0-e63b49eabe2d@gmail.com> In-Reply-To: <20261016-dcphy-rx-v1-v5-0-e63b49eabe2d@gmail.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Guochun Huang , Philipp Zabel Cc: Michael Riesch , Sebastian Reichel , Bryan O'Donoghue , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jason Yang X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792141002; l=1777; i=jason98166@gmail.com; s=20260721; h=from:subject:message-id; bh=4OavUBeyGqaDIQHOgA/IhtahRkKYw5WBMKHlgGZGkLg=; b=v4sInDUQ/7XkIMzK26fj1mNhWedwz2y1jAeJhVW/owd/Y+g6H8l/hQlvpgno7POd/zFYYL10J lVky0MG/7a6BXkIlwekLASsH7MOoF5G3njxjIvRURKOz+XEH0L9NH+L X-Developer-Key: i=jason98166@gmail.com; a=ed25519; pk=xQmD001Q/ooHl39PxyQtusbUQmgbOsSfpFryRVWZ/k4= The MIPI DC-PHY binding takes a second cell that selects the transmitter or the receiver. Switch mipidcphy0 and mipidcphy1 to two cells and let dsi0 and dsi1 select the transmitter. Signed-off-by: Jason Yang --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 376ad04e0786..94d68fd89753 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1788,7 +1788,7 @@ dsi0: dsi@fde20000 { resets = <&cru SRST_P_DSIHOST0>; reset-names = "apb"; power-domains = <&power RK3588_PD_VOP>; - phys = <&mipidcphy0 PHY_TYPE_DPHY>; + phys = <&mipidcphy0 PHY_TYPE_DPHY PHY_DIRECTION_TX>; phy-names = "dcphy"; rockchip,grf = <&vop_grf>; status = "disabled"; @@ -1816,7 +1816,7 @@ dsi1: dsi@fde30000 { resets = <&cru SRST_P_DSIHOST1>; reset-names = "apb"; power-domains = <&power RK3588_PD_VOP>; - phys = <&mipidcphy1 PHY_TYPE_DPHY>; + phys = <&mipidcphy1 PHY_TYPE_DPHY PHY_DIRECTION_TX>; phy-names = "dcphy"; rockchip,grf = <&vop_grf>; status = "disabled"; @@ -3429,7 +3429,7 @@ mipidcphy0: phy@feda0000 { <&cru SRST_P_MIPI_DCPHY0_GRF>, <&cru SRST_S_MIPI_DCPHY0>; reset-names = "m_phy", "apb", "grf", "s_phy"; - #phy-cells = <1>; + #phy-cells = <2>; status = "disabled"; }; @@ -3445,7 +3445,7 @@ mipidcphy1: phy@fedb0000 { <&cru SRST_P_MIPI_DCPHY1_GRF>, <&cru SRST_S_MIPI_DCPHY1>; reset-names = "m_phy", "apb", "grf", "s_phy"; - #phy-cells = <1>; + #phy-cells = <2>; status = "disabled"; }; -- 2.43.0