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[211.23.39.77]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e97e882a20sm6971025ad.62.2026.10.16.01.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2026 01:57:20 -0700 (PDT) From: Jason Yang Date: Fri, 16 Oct 2026 16:56:42 +0800 Subject: [PATCH v5 8/8] arm64: dts: rockchip: add mipi csi-2 receiver nodes for the dcphys on rk3588 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261016-dcphy-rx-v1-v5-8-e63b49eabe2d@gmail.com> References: <20261016-dcphy-rx-v1-v5-0-e63b49eabe2d@gmail.com> In-Reply-To: <20261016-dcphy-rx-v1-v5-0-e63b49eabe2d@gmail.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Guochun Huang , Philipp Zabel Cc: Michael Riesch , Sebastian Reichel , Bryan O'Donoghue , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jason Yang X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792141002; l=2717; i=jason98166@gmail.com; s=20260721; h=from:subject:message-id; bh=45Vrf2/gUP59T6NzCoulPq5BhPIFCtcRAs06OTbCzKM=; b=eV5j0Ku70J/SwIYITZNqaBAM4+oArZCW1gHMYmzwcCjICMvYtJVzPGrN4pNjb2YAnqgdR1JmW QRDZGk+6fb0AGvQEIOdD40NiINRZQcSPgvqp/0vE9+XFZSQzix1cCh3 X-Developer-Key: i=jason98166@gmail.com; a=ed25519; pk=xQmD001Q/ooHl39PxyQtusbUQmgbOsSfpFryRVWZ/k4= The MIPI0 and MIPI1 receiver units are connected to MIPI DCPHY0 and MIPI DCPHY1, whose receiver side is now supported. Add the two nodes and wire them to the VICAP ports. Signed-off-by: Jason Yang --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 68 +++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 94d68fd89753..30bc69a09102 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1516,10 +1516,18 @@ vicap_dvp: port@0 { vicap_mipi0: port@1 { reg = <0x1>; + + vicap_mipi0_input: endpoint { + remote-endpoint = <&csi0_output>; + }; }; vicap_mipi1: port@2 { reg = <0x2>; + + vicap_mipi1_input: endpoint { + remote-endpoint = <&csi1_output>; + }; }; vicap_mipi2: port@3 { @@ -1568,6 +1576,66 @@ vicap_mmu: iommu@fdce0800 { status = "disabled"; }; + csi0: csi@fdd10000 { + compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0xfdd10000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "err1", "err2"; + clocks = <&cru PCLK_CSI_HOST_0>; + phys = <&mipidcphy0 PHY_TYPE_DPHY PHY_DIRECTION_RX>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_P_CSI_HOST_0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_in: port@0 { + reg = <0>; + }; + + csi0_out: port@1 { + reg = <1>; + + csi0_output: endpoint { + remote-endpoint = <&vicap_mipi0_input>; + }; + }; + }; + }; + + csi1: csi@fdd20000 { + compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0xfdd20000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "err1", "err2"; + clocks = <&cru PCLK_CSI_HOST_1>; + phys = <&mipidcphy1 PHY_TYPE_DPHY PHY_DIRECTION_RX>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_P_CSI_HOST_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_in: port@0 { + reg = <0>; + }; + + csi1_out: port@1 { + reg = <1>; + + csi1_output: endpoint { + remote-endpoint = <&vicap_mipi1_input>; + }; + }; + }; + }; + csi2: csi@fdd30000 { compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; reg = <0x0 0xfdd30000 0x0 0x10000>; -- 2.43.0