From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E2AE5187FE; Fri, 16 Oct 2026 16:07:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792166827; cv=none; b=GQtLEZoU4GdPpqMAND9BnLhieX++mGcEJmtWQOGlfNNWei+qpPEAUiT/CJyeqdrm39bIk94Ax156LjfVS99fX3rXsVa1PZdoN0mFnmUJK2g/0y0KGLNXcjb5FfJi7Hh8B/kSVeie3Fyy0vl5TTAtyp0HUISQpnnR2OIKbuT3Xsk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792166827; c=relaxed/simple; bh=Fjg/U77wtX/064bZd+8r9caGC5JdhNR2g80ldhVdTQ8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BtDDWeMD56qy6r1qgzTolNh0x5E3tIVYc3s4eurlfF1tZPe2/uHLEp23DCLraSR+CSvrl7lNday9dy/JJRreQBsyL7AKfueNtIDVDIiKdhM/Y0s43Gt2v2kd0A0y5BVVw7A518DIdyc4Qm3mwasacXzOma4Cl8rIk0Bqg/KIXB8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oSiy7S7F; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oSiy7S7F" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A2B491F000C6; Fri, 16 Oct 2026 16:07:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1792166825; bh=EyhMIFki24z/GS7kQ9MxTJlK5fDdy74J09DSaxUb78g=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=oSiy7S7F/4VWlSrLEKyL8T7zav3l+9kgUofPlfdPeVnZVIL6SOtZQaJE6VFYcbcne u5aJq0t3Ep7iW7oTnJFKvH9aBSl62KQ0S/AcdZm8axc4Dtt5e4tdElIyKfUIfZt3vx OqwY5h5TcOBQkhWwRT42CpUnVkXd1N7vBC8maYs/IRi8ogF782d0aXvdVQpm2nhA7C jz9o3/ipk3gHBGfBT9A+saejHnahRrKRjPjLp31snRs8pMPwtNBDCGE1TdyEHXIIQ4 iAiKjt82eYacWqbo3OtG5R06//eUNIs+QpVfLK0uZca5lIpClHhQtiWfx+70N4jwHJ TAv8ND+khwkrA== From: Sasha Levin To: Thierry Reding , Jonathan Hunter , Lyude Paul , Danilo Krummrich Cc: Sasha Levin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Courbot , Mikko Perttunen , Aaron Kling , Diogo Ivo , Svyatoslav Ryhel , Dmitry Osipenko , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , dri-devel@lists.freedesktop.org, nouveau@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/6] dt-bindings: gpu: nvidia,gk20a: Require the fuse clock Date: Fri, 16 Oct 2026 12:06:54 -0400 Message-ID: <20261016160700.3831336-2-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261016160700.3831336-1-sashal@kernel.org> References: <20261016160700.3831336-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The GM20B on Tegra210 often fails to initialize unless the fuse clock is running while the GPU is powered, and the GPUs on the other Tegra generations are expected to have the same requirement. Tegra194 already describes the fuse clock for its GV11B. Make the fuse clock required for all of them, and list the exact clocks for each GPU instead of allowing either the reference or the fuse clock as the third one: GM20B takes the fuse clock after its reference clock, the others take it after the GPU and power clocks. The nouveau driver keeps treating the fuse clock as optional, so device trees that lack it continue to work as before. Assisted-by: LLM Signed-off-by: Sasha Levin --- .../devicetree/bindings/gpu/nvidia,gk20a.yaml | 52 ++++++++++++++----- 1 file changed, 40 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml index 4d856a8b674c5..af0ada6e02557 100644 --- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml +++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml @@ -39,18 +39,12 @@ properties: Regulator for GPU supply voltage clocks: - minItems: 2 - items: - - description: GPU clock - - description: Power clock - - description: Reference or fuse clock + minItems: 3 + maxItems: 4 clock-names: - minItems: 2 - items: - - const: gpu - - const: pwr - - enum: [ ref, fuse ] + minItems: 3 + maxItems: 4 resets: maxItems: 1 @@ -86,6 +80,39 @@ required: - reset-names allOf: + - if: + properties: + compatible: + contains: + const: nvidia,gm20b + then: + properties: + clocks: + items: + - description: GPU clock + - description: Power clock + - description: Reference clock + - description: Fuse clock + + clock-names: + items: + - const: gpu + - const: pwr + - const: ref + - const: fuse + else: + properties: + clocks: + items: + - description: GPU clock + - description: Power clock + - description: Fuse clock + + clock-names: + items: + - const: gpu + - const: pwr + - const: fuse - if: properties: compatible: @@ -163,8 +190,9 @@ examples: interrupt-names = "stall", "nonstall"; vdd-supply = <&vdd_gpu>; clocks = <&tegra_car TEGRA124_CLK_GPU>, - <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; - clock-names = "gpu", "pwr"; + <&tegra_car TEGRA124_CLK_PLL_P_OUT5>, + <&tegra_car TEGRA124_CLK_FUSE>; + clock-names = "gpu", "pwr", "fuse"; resets = <&tegra_car 184>; reset-names = "gpu"; iommus = <&mc TEGRA_SWGROUP_GPU>; -- 2.53.0