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[180.177.138.120]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ea1501f933sm1697925ad.50.2026.10.19.07.17.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2026 07:17:46 -0700 (PDT) From: Hung-Chun Tseng To: E Shattow Cc: Yixun Lan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/2] riscv: dts: spacemit: k1: mark boot-critical SoC nodes bootph-pre-ram Date: Mon, 19 Oct 2026 22:17:38 +0800 Message-ID: <20261019141740.2077086-1-alan.tseng.cs@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <05e0c9e4-4e27-4114-866a-ec55c33ba349@freeshell.de> References: <20261017180141.3477743-2-alan.tseng.cs@gmail.com> <05e0c9e4-4e27-4114-866a-ec55c33ba349@freeshell.de> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi E, E Shattow wrote: > Drop this last paragraph/sentence or place after scissors line, not for > the commit message itself. Thanks, I will drop it in v3. > Presumably the BootROM does configure all of the above? Mostly. The boot straps select SD, eMMC, SPI NOR or NAND, and the BootROM loads the SPL from there, so the SPL needs the same controllers and the clock and reset controllers behind them. The BootROM also prints to the console UART. i2c8 is different. The BootROM does not touch the PMIC, but the SPL has to set the PMIC regulators over i2c8 before it can bring up DRAM. I will give that as the reason in v3 instead of the U-Boot sentence. The BootROM can also load the SPL over USB fastboot. I left USB out of this series and can add it in a follow-up. Thanks for the review. Hung-Chun