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[180.177.138.120]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-89f8aa31341sm3825523b3a.51.2026.10.19.07.17.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2026 07:17:57 -0700 (PDT) From: Hung-Chun Tseng To: E Shattow Cc: Yixun Lan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/2] riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram Date: Mon, 19 Oct 2026 22:17:48 +0800 Message-ID: <20261019141752.2077207-1-alan.tseng.cs@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <13d6926f-f085-4214-8051-7bf7b5d92b67@freeshell.de> References: <20261017180141.3477743-3-alan.tseng.cs@gmail.com> <13d6926f-f085-4214-8051-7bf7b5d92b67@freeshell.de> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi E, E Shattow wrote: > Does BootROM configure the EEPROM peripheral for access? If not, I > think the justification is weak here to include this. As far as I know it does not. The EEPROM is only read to tell the boards apart, so I will drop the i2c2 and EEPROM tags in v3 and keep the PMIC, whose rails are set before DRAM can be brought up, and the SPI NOR flash, which the BootROM can boot from. Yixun, is there a public description of the BootROM boot flows, or of which peripherals it sets up in each? That would give a clear basis for which nodes to tag. Thanks, Hung-Chun