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Wed, 21 Oct 2026 05:35:31 -0700 (PDT) Received: from FLK-B04Q314.global.tektronix.net ([87.58.102.86]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8a0894b484esm825732b3a.13.2026.10.21.05.35.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 05:35:30 -0700 (PDT) From: Krzysztof Kaszubski To: Frank Li , Sascha Hauer , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Fabio Estevam , Pengutronix Kernel Team , Alice Guo , Peng Fan , imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] ARM: dts: imx7ulp: Add TMP6 PWM node to i.MX7ULP Date: Wed, 21 Oct 2026 14:35:19 +0200 Message-ID: <20261021123522.346317-1-sympthicode@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261021084602.121087-1-sympthicode@gmail.com> References: <20261021084602.121087-1-sympthicode@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the Low Power Timer/Pulse Width Modulation Module 6 (TPM6) node to the i.MX 7ULP device tree. TPM6 is located in the Application Domain (Cortex-A7) at base address 0x40a10000. This enables PWM and timer support for peripherals connected to this domain, such as display backlight controllers. Signed-off-by: Krzysztof Kaszubski --- v2: - Move tpm6 node under ahbbridge1 (bus@40800000), before lpi2c6@40a40000 (reported by DT bot) - Fix author/Signed-off-by email typo (simpthicode -> sympthicode) arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi index 39e37ae9b2b1..6240750b84dc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi @@ -366,6 +366,16 @@ ahbbridge1: bus@40800000 { reg = <0x40800000 0x800000>; ranges; + tpm6: pwm@40a10000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x40a10000 0x1000>; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPTPM6>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + clocks = <&pcc3 IMX7ULP_CLK_LPTPM6>; + #pwm-cells = <3>; + status = "disabled"; + }; + lpi2c6: i2c@40a40000 { compatible = "fsl,imx7ulp-lpi2c"; reg = <0x40a40000 0x10000>; -- 2.43.0