From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=74.125.82.195 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1792637940; b=H6nlsBXLfMFVvYbXUuLhRmnQ2SdsDpTAaXNyDlNw/rT9iagdyZsGn2ZYjodiEOANysts V1vPn3m3WVfEoFMFD+kmP6hC8EkgOsVf/TmQrJbMhz/MCQy+EBVYqtl1/qdqKtm25oMiN PEz4OKTHDJ8KIhEUr48bjPvljBbOpLqK7f8UHD/wh0Z0p2ZDyw3fcSOLwA5titWE7H5QN sMuIiGLn1EL419wSGF2wtUrlmED8tokGooNR3M48Qq0xBF9CxrjRNRrqcHoD/68tz8JAw 84oRYWkEoeiGI6PzYFqCvJL/olmQb6LzxRxT8hjHWlJxoXdVHRd2rKahlXVFwsc6ptg== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1792637940; h=DMARC-Filter:Received:DKIM-Signature:X-Google-DKIM-Signature: X-Forwarded-Encrypted:X-Gm-Message-State:X-Gm-Gg:X-Received:Received: From:To:Cc:Subject:Date:Message-ID:X-Mailer:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding; bh=E+chekywn+zjR8qKfFmlr4rUPqe8P6DWzkjYSgfwJdo=; b=wn/XqvJ3jZT7mAidO8t+QHrz4W7HztHFuoHlz36oZl/6x6EZSNh4VX6hFZu0UKueFuLQ Z3bDJQAvHhCANvfCJbPGkNHTZzZcWLKLZgUOhRAqpnBuXfbkdzF50rHrOv0LXBrZfgVOP rKBfaEWiZQ/SCc21zRTAFUdlPkdYeS26kWKjAuRmiYTVFkwrClXDM2NLMEAfU5QvqFCrP qE03sWFHbZDl45MJhSN8eYlMPLTizqrydBWIcLLC14KF4hwpah/n+ww2L6bbuM3pGDq+s d83Vybs+c7pjf937JfcCAzFqE2/yY2UmuuNFqfkxPsDKJxDTD7Uip8kh3w5SYRqBEJQ== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20251104 header.b=o7+p0OQ9; arc=none smtp.remote-ip=74.125.82.195 Received: from mail-dy1-f195.google.com (mail-dy1-f195.google.com [74.125.82.195]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A01F606A31A for ; Thu, 22 Oct 2026 02:59:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org 5A01F606A31A Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20251104 header.b=o7+p0OQ9 Received: by mail-dy1-f195.google.com with SMTP id 5a478bee46e88-35943f55c06so610616eec.0 for ; Wed, 21 Oct 2026 19:59:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1792637939; x=1793242739; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=E+chekywn+zjR8qKfFmlr4rUPqe8P6DWzkjYSgfwJdo=; b=o7+p0OQ9P7X/6I/FftPKNs/8Xfj5B6WQI4v4477jZGnkoH6FrHP0wFHqU7JYH76JHH TXUL2GYwHOCFVjuylxta4AylGNQxKu4ngdATkVq1kWdq3lumM7QebfDxCPjyryPqgsKX YEKWU4R3fwwywglTXlEd7ev1T2Pa7OXrsExKzjsYGA2zrGPvqAFyFFsIAr1712U0xvIe 1FH1hcH92R6Ry2qcX9roNtXQDWiYtiJaheVXRjTBY4sUGVbntdgQD5uEELmC6i1iRTee zUTRqMqv1OzRj0UhBkh2dEzUZGeM/lNf7EjOskqfLljTJnZzWj0UebjJCBSa4G96nB3V CPRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792637939; x=1793242739; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=E+chekywn+zjR8qKfFmlr4rUPqe8P6DWzkjYSgfwJdo=; b=2Lc8V2dKszeAB6uaelOdVcknVF3V6T8LN5koSfrl6HREj3hlHnKJ9HzbLO1ZyuqRe0 SwwDfLLWQgz14zvQ0/Z5kTb6PG60jGY66rNhYRgngUalJHhzx34J0EIfYGpeaqGztfDw +wisa58Bnc5S1iWx41Tq3XMba76V0oN9sHkCr7KNvpMHXIEegODh5wC7tguV5LhdGIfJ Cw99uCPCpm9SPz2QuhLaMfPUvxXm2AyHlAtzAO4MnEZzGINzpol4+++Ss3HL8qEWsPG5 ZTrcSGQW+w0J/doelbCRPjehJp10JcDxUwRCAPaNYpNEYtw0erzRwgJpsT4jXDpVE8fL /OLg== X-Forwarded-Encrypted: i=1; AKwUvBye/XNdtZqQPUHPQTLGZkoR7pFiSEho0mhRxqifOiEwf4L8xS4X6y8UKe4iUNJckrbIeXXH39ntblnw@vger.kernel.org X-Gm-Message-State: AFq9FYIeVLG0S2hEyu1zHupjSP2j+XTAMTkVJ7OszvwocIwyOwIg05iN uFxGeEQgJJdrrO166NVDMBeY5Jj9qmugE5QhYHBuNmEa/o3055ClufFv X-Gm-Gg: AYBFou3t195c/bVl02uHmDQx4pC0Cb+GABz4oae4/KFBQ+7bcjHZKF0b2zWO1OUxjZG Tb2wGs5TY0CHIFQLKNaHoJGpgZ9lZ5TQWQQF33HJ6FScdwTBgM37JUc5UABAmmVjuY8m/1hUnBn 3+FL6DLGmPv+4jCPbpkvV4Vi404IpLOB7139xxFahJF6+9x7PZ2aAiFU3uiAbESIMGgXbRzGeIM O7XfTVb0miyktH4OAW1KnSOrmG4Bxl9ZOdpWNv1eH1dS7+ALGSCBoxq7lrjgmMcBbMNpcaCtBX7 lRWQuVfXp6uZuDk+ozmVez5PvDRi4/8UQG5w7mfHk937J+RwDWScfJ+KOff1Z+A9HmxAH14iC88 qwArt5OnZs8f9eYv6+TKBrD3ipxlvzSkkqyZwtIE5RxJnKfML+h05B0s2FDwTRhIg53XXWsM50d IftOr4GHdk5IOHpuL762c6HxRwgRy8Esg53ySFZtPbxfewA8Z42EZrKiAiA8EUcA6mQxmCxDo47 IikoCCc6sJZdLGU7CLD5LUwGHAecOszMZjeRuf8Z83I9S0djKLhCw== X-Received: by 2002:a05:7300:d407:b0:362:2e2f:c261 with SMTP id 5a478bee46e88-368b15180d8mr1324129eec.27.1792637938909; Wed, 21 Oct 2026 19:58:58 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36740cc8c6dsm13029572eec.12.2026.10.21.19.58.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 19:58:58 -0700 (PDT) From: Coia Prant To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Lin , David Heidelberg , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Coia Prant Subject: [PATCH v11 1/3] arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes Date: Thu, 22 Oct 2026 10:58:42 +0800 Message-ID: <20261022025844.150320-2-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261022025844.150320-1-coiaprant@gmail.com> References: <20261022025844.150320-1-coiaprant@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The RK3568 SoC integrates a Synopsys DesignWare XPCS that provides the Physical Coding Sublayer for 1000BASE-X, SGMII, and QSGMII interfaces via its four MII ports. Add the XPCS device node to the SoC device tree. The XPCS device is accessed via the APB3 bus at 0xfda00000 and requires the CSR clock (PCLK_XPCS) for register access and the EEE clock (CLK_XPCS_EEE) for Energy Efficient Ethernet operation. The PD_PIPE power domain must be enabled before any register access. Also add two fixed-clock nodes (clock-xpcs-gmac0 and clock-xpcs-gmac1, labelled clk_gmac0_xpcs_mii and clk_gmac1_xpcs_mii) providing the 125 MHz reference clock for the GMACs when operating with XPCS. Their clock-output-names match the CRU mux parent names in clk-rk3568.c, so boards can reparent SCLK_GMAC0_RX_TX / SCLK_GMAC1_RX_TX through assigned-clock-parents. The XPCS node is disabled by default and must be enabled at the board level when 1000BASE-X/SGMII/QSGMII is in use. The fixed-clock nodes are always present and do not have a status property, as they are static clock sources. The XPCS node requires a reference to the appropriate Naneng Combo PHY via the phys property. dtbs_check only validates required properties for enabled nodes, so the SoC dtsi does not provide phys: boards that enable the XPCS must supply it, since the SerDes link is a board-level design choice (combphy1 on some boards, combphy2 on others). Signed-off-by: Coia Prant --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 3bc653f027f1f..20a72785adbc2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -8,6 +8,20 @@ / { compatible = "rockchip,rk3568"; + clk_gmac0_xpcs_mii: clock-xpcs-gmac0 { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clk_gmac0_xpcs_mii"; + #clock-cells = <0>; + }; + + clk_gmac1_xpcs_mii: clock-xpcs-gmac1 { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clk_gmac1_xpcs_mii"; + #clock-cells = <0>; + }; + cpu0_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -110,6 +124,15 @@ sata0: sata@fc000000 { status = "disabled"; }; + xpcs: ethernet-pcs@fda00000 { + compatible = "rockchip,rk3568-xpcs"; + reg = <0x0 0xfda00000 0x0 0x200000>; + clocks = <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; + clock-names = "csr", "eee"; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + pipe_phy_grf0: syscon@fdc70000 { compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; reg = <0x0 0xfdc70000 0x0 0x1000>; -- 2.47.3