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Fri, 23 Oct 2026 00:29:43 -0700 (PDT) Received: from localhost.localdomain ([218.194.41.155]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ea7af6a466sm6858715ad.9.2026.10.23.00.29.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 00:29:43 -0700 (PDT) From: ShiTou Hong X-Google-Original-From: ShiTou Hong To: andersson@kernel.org, konradybcio@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, ShiTou Hong , KancyJoe Subject: [PATCH 4/6] arm64: dts: qcom: sm8250-hdk: Enable the PCIe ports Date: Fri, 23 Oct 2026 15:28:30 +0800 Message-ID: <20261023072832.2642647-4-dc_redstone@outlook.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261023072832.2642647-1-dc_redstone@outlook.com> References: <20261023072832.2642647-1-dc_redstone@outlook.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The sm8250-hdk has 2 PCIe ports which are not enabled in the dts. The pcie0 is for the on-board ath11k WiFi/BT module; while the pcie2 is for the M.2 connector. Add the 3V3 regulator node for pcie2. Enable the 2 pcie controllers and phys. Co-developed-by: KancyJoe Signed-off-by: ShiTou Hong --- arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index 7a2903941..bd9b90fbc 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -57,6 +57,13 @@ lt9611_1v2: lt9611-vdd12-regulator { regulator-max-microvolt = <1200000>; }; + vreg_3p3: vreg-3p3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + vreg_s6c_0p88: smpc6-regulator { compatible = "regulator-fixed"; regulator-name = "vreg_s6c_0p88"; @@ -722,3 +729,24 @@ pm8150b_typec_sbu_out: endpoint { &usb_1_qmpphy_dp_in { remote-endpoint = <&mdss_dp_out>; }; + +&pcie0 { + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; + status = "okay"; +}; + +&pcie2 { + status = "okay"; + vddpe-3v3-supply = <&vreg_3p3>; +}; + +&pcie2_phy { + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; + status = "okay"; +}; -- 2.47.3