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[180.177.138.120]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3adeba38910sm1392312a91.1.2026.10.24.02.26.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Oct 2026 02:26:07 -0700 (PDT) From: Hung-Chun Tseng To: Yixun Lan , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , E Shattow , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] riscv: dts: spacemit: k1: mark boot-critical SoC nodes bootph-pre-ram Date: Sat, 24 Oct 2026 17:25:57 +0800 Message-ID: <20261024092558.143621-2-alan.tseng.cs@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261024092558.143621-1-alan.tseng.cs@gmail.com> References: <20261024092558.143621-1-alan.tseng.cs@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The K1 BootROM loads the next boot stage from SD, eMMC or SPI NOR into SRAM, and that stage brings up DRAM. To do so it needs the fixed clocks, the clock and reset controllers, the console UART, the boot media controllers (sdhci0, eMMC and QSPI), and two I2C buses that every K1 board wires the same way: i2c2 to the EEPROM that holds the DRAM configuration, and i2c8 to the PMIC that supplies the SoC. Mark these nodes bootph-pre-ram, the phase that sets up SDRAM. Reviewed-by: E Shattow Signed-off-by: Hung-Chun Tseng --- arch/riscv/boot/dts/spacemit/k1.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 3fabfd3411..8a954f56a9 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -322,6 +322,7 @@ cluster1_l2_cache: l2-cache1 { clocks { vctcxo_1m: clock-1m { compatible = "fixed-clock"; + bootph-pre-ram; clock-frequency = <1000000>; clock-output-names = "vctcxo_1m"; #clock-cells = <0>; @@ -329,6 +330,7 @@ vctcxo_1m: clock-1m { vctcxo_24m: clock-24m { compatible = "fixed-clock"; + bootph-pre-ram; clock-frequency = <24000000>; clock-output-names = "vctcxo_24m"; #clock-cells = <0>; @@ -336,6 +338,7 @@ vctcxo_24m: clock-24m { vctcxo_3m: clock-3m { compatible = "fixed-clock"; + bootph-pre-ram; clock-frequency = <3000000>; clock-output-names = "vctcxo_3m"; #clock-cells = <0>; @@ -343,6 +346,7 @@ vctcxo_3m: clock-3m { osc_32k: clock-32k { compatible = "fixed-clock"; + bootph-pre-ram; clock-frequency = <32768>; clock-output-names = "osc_32k"; #clock-cells = <0>; @@ -544,6 +548,7 @@ i2c1: i2c@d4011000 { i2c2: i2c@d4012000 { compatible = "spacemit,k1-i2c"; reg = <0x0 0xd4012000 0x0 0x38>; + bootph-pre-ram; #address-cells = <1>; #size-cells = <0>; clocks = <&syscon_apbc CLK_TWSI2>, @@ -586,6 +591,7 @@ i2c5: i2c@d4013800 { syscon_apbc: system-controller@d4015000 { compatible = "spacemit,k1-syscon-apbc"; reg = <0x0 0xd4015000 0x0 0x1000>; + bootph-pre-ram; clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; clock-names = "osc", "vctcxo_1m", "vctcxo_3m", @@ -726,6 +732,7 @@ i2c7: i2c@d401d000 { i2c8: i2c@d401d800 { compatible = "spacemit,k1-i2c"; reg = <0x0 0xd401d800 0x0 0x38>; + bootph-pre-ram; #address-cells = <1>; #size-cells = <0>; clocks = <&syscon_apbc CLK_TWSI8>, @@ -857,6 +864,7 @@ pwm19: pwm@d4022c00 { syscon_mpmu: system-controller@d4050000 { compatible = "spacemit,k1-syscon-mpmu"; reg = <0x0 0xd4050000 0x0 0x209c>; + bootph-pre-ram; clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; clock-names = "osc", "vctcxo_1m", "vctcxo_3m", @@ -869,6 +877,7 @@ syscon_mpmu: system-controller@d4050000 { pll: clock-controller@d4090000 { compatible = "spacemit,k1-pll"; reg = <0x0 0xd4090000 0x0 0x1000>; + bootph-pre-ram; clocks = <&vctcxo_24m>; spacemit,mpmu = <&syscon_mpmu>; #clock-cells = <1>; @@ -877,6 +886,7 @@ pll: clock-controller@d4090000 { syscon_apmu: system-controller@d4282800 { compatible = "spacemit,k1-syscon-apmu"; reg = <0x0 0xd4282800 0x0 0x400>; + bootph-pre-ram; clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; clock-names = "osc", "vctcxo_1m", "vctcxo_3m", @@ -956,6 +966,7 @@ uart0: serial@d4017000 { compatible = "spacemit,k1-uart", "intel,xscale-uart"; reg = <0x0 0xd4017000 0x0 0x100>; + bootph-pre-ram; clocks = <&syscon_apbc CLK_UART0>, <&syscon_apbc CLK_UART0_BUS>; clock-names = "core", "bus"; @@ -1085,6 +1096,7 @@ qspi: spi@d420c000 { reg = <0x0 0xd420c000 0x0 0x1000>, <0x0 0xb8000000 0x0 0xc00000>; reg-names = "QuadSPI", "QuadSPI-memory"; + bootph-pre-ram; clocks = <&syscon_apmu CLK_QSPI_BUS>, <&syscon_apmu CLK_QSPI>; clock-names = "qspi_en", "qspi"; @@ -1328,6 +1340,7 @@ usb_dwc3: usb@c0a00000 { sdhci0: mmc@d4280000 { compatible = "spacemit,k1-sdhci"; reg = <0x0 0xd4280000 0x0 0x200>; + bootph-pre-ram; clocks = <&syscon_apmu CLK_SDH_AXI>, <&syscon_apmu CLK_SDH0>; clock-names = "core", "io"; @@ -1341,6 +1354,7 @@ sdhci0: mmc@d4280000 { emmc: mmc@d4281000 { compatible = "spacemit,k1-sdhci"; reg = <0x0 0xd4281000 0x0 0x200>; + bootph-pre-ram; clocks = <&syscon_apmu CLK_SDH_AXI>, <&syscon_apmu CLK_SDH2>; clock-names = "core", "io"; -- 2.43.0