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Sat, 24 Oct 2026 21:21:40 -0700 (PDT) Received: from ZephyrLabServer.internal ([165.162.64.148]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-198a0f81ea9sm14037825c88.11.2026.10.24.21.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Oct 2026 21:21:39 -0700 (PDT) From: John Macias To: andersson@kernel.org, mathieu.poirier@linaro.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, manikanta.mylavarapu@oss.qualcomm.com, varadarajan.narayanan@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH RFC 1/2] dt-bindings: remoteproc: qcom: wcss-sec: add IPQ8074 Date: Sat, 24 Oct 2026 21:20:59 -0700 Message-ID: <20261025042100.1356088-2-dencity7@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261025042100.1356088-1-dencity7@gmail.com> References: <20261025042100.1356088-1-dencity7@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Document the IPQ8074 WCSS secure PIL. It needs the PRNG AHB clock, so move the clock names from the top level into the per-compatible rules; IPQ5018, IPQ5332 and IPQ9574 keep the same clock constraints. IPQ8074 firmware ships the M3 image separately from Q6, with its own load address, and some boards place it in its own reserved region with board data between the two. Allow IPQ8074 to name its regions "q6" and "m3" and to give the M3 firmware name as a second firmware-name entry. Without memory-region-names a single region holds the firmware, as for the other compatibles, which keep their existing constraints. Assisted-by: LLM Signed-off-by: John Macias --- .../remoteproc/qcom,ipq5018-wcss-sec-pil.yaml | 96 +++++++++++++++++-- 1 file changed, 88 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,ipq5018-wcss-sec-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,ipq5018-wcss-sec-pil.yaml index 1ec8df60d..89d648769 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,ipq5018-wcss-sec-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,ipq5018-wcss-sec-pil.yaml @@ -18,14 +18,17 @@ properties: enum: - qcom,ipq5018-wcss-sec-pil - qcom,ipq5332-wcss-sec-pil + - qcom,ipq8074-wcss-sec-pil - qcom,ipq9574-wcss-sec-pil reg: maxItems: 1 firmware-name: - maxItems: 1 - description: Firmware name for the Hexagon core + minItems: 1 + items: + - description: Firmware name for the Hexagon core + - description: Firmware name for the M3 core, loaded separately interrupts: items: @@ -45,15 +48,11 @@ properties: clocks: minItems: 1 - items: - - description: sleep clock - - description: AHB interconnect clock + maxItems: 2 clock-names: minItems: 1 - items: - - const: sleep - - const: interconnect + maxItems: 2 mboxes: items: @@ -74,8 +73,18 @@ properties: - const: shutdown memory-region: + minItems: 1 items: - description: Q6 reserved region + - description: M3 reserved region + + memory-region-names: + description: + Present only when the M3 firmware is loaded into its own reserved + region. Without it, a single region holds the firmware. + items: + - const: q6 + - const: m3 glink-edge: $ref: /schemas/remoteproc/qcom,glink-edge.yaml# @@ -131,6 +140,40 @@ allOf: - clocks - clock-names + - if: + properties: + compatible: + contains: + const: qcom,ipq8074-wcss-sec-pil + then: + properties: + clocks: + items: + - description: PRNG AHB clock + clock-names: + items: + - const: prng + required: + - clocks + - clock-names + else: + properties: + firmware-name: + maxItems: 1 + memory-region: + maxItems: 1 + memory-region-names: false + + - if: + required: + - memory-region-names + then: + properties: + firmware-name: + minItems: 2 + memory-region: + minItems: 2 + - if: properties: compatible: @@ -176,3 +219,40 @@ examples: mboxes = <&apcs_glb 8>; }; }; + + - | + #include + + remoteproc@cd00000 { + compatible = "qcom,ipq8074-wcss-sec-pil"; + reg = <0x0cd00000 0x4040>; + firmware-name = "ath11k/IPQ8074/hw1.0/q6_fw.mdt", + "ath11k/IPQ8074/hw1.0/m3_fw.mdt"; + interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 1 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 2 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 3 IRQ_TYPE_NONE>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&gcc 50>; + clock-names = "prng"; + + qcom,smem-states = <&wcss_smp2p_out 1>, + <&wcss_smp2p_out 0>; + qcom,smem-state-names = "stop", + "shutdown"; + memory-region = <&q6_region>, <&m3_region>; + memory-region-names = "q6", "m3"; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + }; -- 2.47.3