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[180.177.138.120]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cd8ccc21017sm989192a12.10.2026.10.25.20.38.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Oct 2026 20:38:17 -0700 (PDT) From: Hung-Chun Tseng To: E Shattow Cc: dlan@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 0/2] riscv: dts: spacemit: mark K1 boot nodes bootph-pre-ram Date: Mon, 26 Oct 2026 11:38:11 +0800 Message-ID: <20261026033813.432250-1-alan.tseng.cs@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <813d3f4a-66a9-48df-b9de-6a46b9388d0a@freeshell.de> References: <20261024092558.143621-1-alan.tseng.cs@gmail.com> <813d3f4a-66a9-48df-b9de-6a46b9388d0a@freeshell.de> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi E, On 10/24/26 07:45, E Shattow wrote: > Split the patches in this series so we have a clearly defined initial > changeset that does "Extend the BootROM configured peripherals to device > tree bootph-pre-ram hints for any SPL loaded by that BootROM in SD, > eMMC, and SPI NOR boot modes". Thanks, that makes sense. For v4 I plan this split: 1. BootROM: the fixed clocks, the clock and reset controllers, uart0, sdhci0, emmc and qspi in k1.dtsi, and the SPI NOR flash@0 in the board files. 2. DRAM setup, as an add-on for Yixun to take or leave: i2c2 and i2c8 in k1.dtsi, and the EEPROM, the PMIC and its buck1, buck3 and aldo1 in the board files. > Capture all the BootROM SPL loader flows > that we can understand (USB missing currently? please add this) USB download mode goes through the OTG port (FDL button, then "fastboot stage"), but mainline has no node for the USB2 OTG controller behind it yet. The DWC3 is a different controller. So there is nothing to tag for USB today, and I'd add it once that node lands. Yixun, could you confirm that the BootROM uses that OTG controller for USB download, and that it does not touch the DWC3? Does this split look right to you? I'll send v4 after the merge window. Thanks, Hung-Chun