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[93.34.92.187]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4a35a0cc374sm190382825e9.9.2026.10.26.02.57.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 02:57:35 -0700 (PDT) From: Christian Marangi To: Matthias Brugger , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Christian Marangi , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/9] arm64: dts: airoha: en7581: reorder nodes following incremental regs Date: Mon, 26 Oct 2026 10:57:07 +0100 Message-ID: <20261026095727.31708-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261026095727.31708-1-ansuelsmth@gmail.com> References: <20261026095727.31708-1-ansuelsmth@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Reorder nods position following incremental register. This is to tidy things up and no additional code is added. Signed-off-by: Christian Marangi --- arch/arm64/boot/dts/airoha/en7581.dtsi | 246 ++++++++++++------------- 1 file changed, 123 insertions(+), 123 deletions(-) diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi index ff6908a76e8e..83b30a340950 100644 --- a/arch/arm64/boot/dts/airoha/en7581.dtsi +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi @@ -173,18 +173,6 @@ spi_nand: nand@0 { }; }; - scuclk: clock-controller@1fb00000 { - compatible = "airoha,en7581-scu"; - reg = <0x0 0x1fb00000 0x0 0x970>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pbus_csr: syscon@1fbe3400 { - compatible = "airoha,en7581-pbus-csr", "syscon"; - reg = <0x0 0x1fbe3400 0x0 0xff>; - }; - pciephy: phy@1fa5a000 { compatible = "airoha,en7581-pcie-phy"; reg = <0x0 0x1fa5a000 0x0 0xfff>, @@ -199,6 +187,129 @@ pciephy: phy@1fa5a000 { #phy-cells = <0>; }; + rng@1faa1000 { + compatible = "airoha,en7581-trng"; + reg = <0x0 0x1faa1000 0x0 0xc04>; + interrupts = ; + }; + + scuclk: clock-controller@1fb00000 { + compatible = "airoha,en7581-scu"; + reg = <0x0 0x1fb00000 0x0 0x970>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + eth: ethernet@1fb50000 { + compatible = "airoha,en7581-eth"; + reg = <0 0x1fb50000 0 0x2600>, + <0 0x1fb54000 0 0x2000>, + <0 0x1fb56000 0 0x2000>; + reg-names = "fe", "qdma0", "qdma1"; + + resets = <&scuclk EN7581_FE_RST>, + <&scuclk EN7581_FE_PDMA_RST>, + <&scuclk EN7581_FE_QDMA_RST>, + <&scuclk EN7581_XSI_MAC_RST>, + <&scuclk EN7581_DUAL_HSI0_MAC_RST>, + <&scuclk EN7581_DUAL_HSI1_MAC_RST>, + <&scuclk EN7581_HSI_MAC_RST>, + <&scuclk EN7581_XFP_MAC_RST>; + reset-names = "fe", "pdma", "qdma", + "xsi-mac", "hsi0-mac", "hsi1-mac", + "hsi-mac", "xfp-mac"; + + interrupts = , + , + , + , + , + , + , + , + , + ; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + gdm1: ethernet@1 { + compatible = "airoha,eth-mac"; + reg = <1>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + }; + + pbus_csr: syscon@1fbe3400 { + compatible = "airoha,en7581-pbus-csr", "syscon"; + reg = <0x0 0x1fbe3400 0x0 0xff>; + }; + + uart1: serial@1fbf0000 { + compatible = "ns16550"; + reg = <0x0 0x1fbf0000 0x0 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clock-frequency = <1843200>; + }; + + system-controller@1fbf0200 { + compatible = "airoha,en7581-gpio-sysctl", "syscon", + "simple-mfd"; + reg = <0x0 0x1fbf0200 0x0 0xc0>; + + en7581_pinctrl: pinctrl { + compatible = "airoha,en7581-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + i2c0: i2c@1fbf8000 { + compatible = "mediatek,mt7621-i2c"; + reg = <0x0 0x1fbf8000 0x0 0x100>; + + resets = <&scuclk EN7581_I2C2_RST>; + + clocks = <&clk20m>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@1fbf8100 { + compatible = "mediatek,mt7621-i2c"; + reg = <0x0 0x1fbf8100 0x0 0x100>; + + resets = <&scuclk EN7581_I2C_MASTER_RST>; + + clocks = <&clk20m>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + pcie0: pcie@1fc00000 { compatible = "airoha,en7581-pcie"; device_type = "pci"; @@ -284,116 +395,5 @@ pcie_intc1: interrupt-controller { #interrupt-cells = <1>; }; }; - - uart1: serial@1fbf0000 { - compatible = "ns16550"; - reg = <0x0 0x1fbf0000 0x0 0x30>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = ; - clock-frequency = <1843200>; - }; - - rng@1faa1000 { - compatible = "airoha,en7581-trng"; - reg = <0x0 0x1faa1000 0x0 0xc04>; - interrupts = ; - }; - - system-controller@1fbf0200 { - compatible = "airoha,en7581-gpio-sysctl", "syscon", - "simple-mfd"; - reg = <0x0 0x1fbf0200 0x0 0xc0>; - - en7581_pinctrl: pinctrl { - compatible = "airoha,en7581-pinctrl"; - - interrupt-parent = <&gic>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - i2c0: i2c@1fbf8000 { - compatible = "mediatek,mt7621-i2c"; - reg = <0x0 0x1fbf8000 0x0 0x100>; - - resets = <&scuclk EN7581_I2C2_RST>; - - clocks = <&clk20m>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c1: i2c@1fbf8100 { - compatible = "mediatek,mt7621-i2c"; - reg = <0x0 0x1fbf8100 0x0 0x100>; - - resets = <&scuclk EN7581_I2C_MASTER_RST>; - - clocks = <&clk20m>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - eth: ethernet@1fb50000 { - compatible = "airoha,en7581-eth"; - reg = <0 0x1fb50000 0 0x2600>, - <0 0x1fb54000 0 0x2000>, - <0 0x1fb56000 0 0x2000>; - reg-names = "fe", "qdma0", "qdma1"; - - resets = <&scuclk EN7581_FE_RST>, - <&scuclk EN7581_FE_PDMA_RST>, - <&scuclk EN7581_FE_QDMA_RST>, - <&scuclk EN7581_XSI_MAC_RST>, - <&scuclk EN7581_DUAL_HSI0_MAC_RST>, - <&scuclk EN7581_DUAL_HSI1_MAC_RST>, - <&scuclk EN7581_HSI_MAC_RST>, - <&scuclk EN7581_XFP_MAC_RST>; - reset-names = "fe", "pdma", "qdma", - "xsi-mac", "hsi0-mac", "hsi1-mac", - "hsi-mac", "xfp-mac"; - - interrupts = , - , - , - , - , - , - , - , - , - ; - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - gdm1: ethernet@1 { - compatible = "airoha,eth-mac"; - reg = <1>; - phy-mode = "internal"; - status = "disabled"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - }; }; }; -- 2.55.0