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[93.34.92.187]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4a35a0cc374sm190382825e9.9.2026.10.26.02.57.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 02:57:36 -0700 (PDT) From: Christian Marangi To: Matthias Brugger , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Christian Marangi , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/9] arm64: dts: airoha: en7581: add CPU OPP and scaling nodes Date: Mon, 26 Oct 2026 10:57:08 +0100 Message-ID: <20261026095727.31708-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261026095727.31708-1-ansuelsmth@gmail.com> References: <20261026095727.31708-1-ansuelsmth@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add required CPU OPP and PD nodes to support CPU frequency scaling. Signed-off-by: Christian Marangi --- arch/arm64/boot/dts/airoha/en7581.dtsi | 177 ++++++++++++++++++++++++- 1 file changed, 173 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi index 83b30a340950..c5a335086741 100644 --- a/arch/arm64/boot/dts/airoha/en7581.dtsi +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi @@ -74,8 +74,12 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; + operating-points-v2 = <&cpu_opp_table>; enable-method = "psci"; - clock-frequency = <80000000>; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "perf"; next-level-cache = <&l2>; }; @@ -83,8 +87,12 @@ cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; + operating-points-v2 = <&cpu_opp_table>; enable-method = "psci"; - clock-frequency = <80000000>; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "perf"; next-level-cache = <&l2>; }; @@ -92,8 +100,12 @@ cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; + operating-points-v2 = <&cpu_opp_table>; enable-method = "psci"; - clock-frequency = <80000000>; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "perf"; next-level-cache = <&l2>; }; @@ -101,8 +113,12 @@ cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; + operating-points-v2 = <&cpu_opp_table>; enable-method = "psci"; - clock-frequency = <80000000>; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "perf"; next-level-cache = <&l2>; }; @@ -115,6 +131,159 @@ l2: l2-cache { }; }; + cpufreq: cpufreq { + compatible = "airoha,en7581-cpufreq"; + + operating-points-v2 = <&cpu_smcc_opp_table>; + + #power-domain-cells = <0>; + #clock-cells = <0>; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&smcc_opp0>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + required-opps = <&smcc_opp1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&smcc_opp2>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&smcc_opp3>; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + required-opps = <&smcc_opp4>; + }; + + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + required-opps = <&smcc_opp5>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + required-opps = <&smcc_opp6>; + }; + + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + required-opps = <&smcc_opp7>; + }; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + required-opps = <&smcc_opp8>; + }; + + opp-950000000 { + opp-hz = /bits/ 64 <950000000>; + required-opps = <&smcc_opp9>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + required-opps = <&smcc_opp10>; + }; + + opp-1050000000 { + opp-hz = /bits/ 64 <1050000000>; + required-opps = <&smcc_opp11>; + }; + + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + required-opps = <&smcc_opp12>; + }; + + opp-1150000000 { + opp-hz = /bits/ 64 <1150000000>; + required-opps = <&smcc_opp13>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + required-opps = <&smcc_opp14>; + }; + }; + + cpu_smcc_opp_table: opp-table-smcc { + compatible = "operating-points-v2"; + + smcc_opp0: opp-0 { + opp-level = <0>; + }; + + smcc_opp1: opp-1 { + opp-level = <1>; + }; + + smcc_opp2: opp-2 { + opp-level = <2>; + }; + + smcc_opp3: opp-3 { + opp-level = <3>; + }; + + smcc_opp4: opp-4 { + opp-level = <4>; + }; + + smcc_opp5: opp-5 { + opp-level = <5>; + }; + + smcc_opp6: opp-6 { + opp-level = <6>; + }; + + smcc_opp7: opp-7 { + opp-level = <7>; + }; + + smcc_opp8: opp-8 { + opp-level = <8>; + }; + + smcc_opp9: opp-9 { + opp-level = <9>; + }; + + smcc_opp10: opp-10 { + opp-level = <10>; + }; + + smcc_opp11: opp-11 { + opp-level = <11>; + }; + + smcc_opp12: opp-12 { + opp-level = <12>; + }; + + smcc_opp13: opp-13 { + opp-level = <13>; + }; + + smcc_opp14: opp-14 { + opp-level = <14>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; -- 2.55.0