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[88.207.14.234]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a35a00e1b0sm152200695e9.3.2026.10.26.05.09.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 05:09:32 -0700 (PDT) From: Robert Marko To: andersson@kernel.org, abelvesa@kernel.org, sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, taniya.das@oss.qualcomm.com, ansuelsmth@gmail.com, john@phrozen.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 2/4] dt-bindings: clocks: qcom,gcc-ipq8074: Allow CMN PLL bias clocks Date: Mon, 26 Oct 2026 13:08:13 +0100 Message-ID: <20261026120920.1667982-2-robimarko@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261026120920.1667982-1-robimarko@gmail.com> References: <20261026120920.1667982-1-robimarko@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit CMN PLL in IPQ8074 provides 2 fixed clocks to the GCC clock controller. In order to describe this in DTS, allow passing them as the inputs to GCC. This has a benefit that it avoids doing a global matching by name. Signed-off-by: Robert Marko --- Changes in v2: - Keep the existing four-clock form valid with minItems: 4. - Drop the _clk suffix from the new GCC input names. - Correct the NSS NoC bias clock description to 461.5 MHz. .../devicetree/bindings/clock/qcom,gcc-ipq8074.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml index 00d7df75b3d6..1c9854a5c572 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml @@ -24,18 +24,24 @@ properties: const: qcom,gcc-ipq8074 clocks: + minItems: 4 items: - description: board XO clock - description: sleep clock - description: Gen3 QMP PCIe PHY PIPE clock - description: Gen2 QMP PCIe PHY PIPE clock + - description: 300 MHz bias clock from CMN PLL + - description: 461.5 MHz NSS NoC bias clock from CMN PLL clock-names: + minItems: 4 items: - const: xo - const: sleep_clk - const: pcie0_pipe - const: pcie1_pipe + - const: bias_pll_cc + - const: bias_pll_nss_noc required: - compatible -- 2.56.0