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[144.49.247.13]) by smtp-relay.gmail.com with ESMTPS id 98e67ed59e1d1-3ae406dc8fbsm320199a91.1.2026.10.26.12.18.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 26 Oct 2026 12:18:05 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qv1-f72.google.com with SMTP id 6a1803df08f44-91c44b8fed1so61931806d6.1 for ; Mon, 26 Oct 2026 12:18:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1793042284; x=1793647084; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=AaqGunwSleeDLPx2z6NkDc6zUunPgMcaEWPlGCr1dr4=; b=Tn1WMVIBGSyvEXQW6ghXykDqjZsixbqHSgiyjXQtlTsblqZtOCn6qc4YHUg1RknSqu fGRmg2itEUqXrX0YuwUnu1Rkvox2ehEV0ura38GsFIkufp8ABgnIv4E3BYx1e2oMi/Pk N2YsiTY638Thf3Znlxj6q+CwLLO/Nwois6aPI= X-Forwarded-Encrypted: i=1; AKwUvBxfzlGgawycsO2xQyELaNIcg3C961IIqkktOvnNjDNK2+Rsh7ypuLZEpJoiIc0R3DHOKSoQAV2R7Eoe@vger.kernel.org X-Received: by 2002:a05:6214:5701:b0:914:5769:dcee with SMTP id 6a1803df08f44-91c48e36c9emr119686386d6.17.1793042284482; Mon, 26 Oct 2026 12:18:04 -0700 (PDT) X-Received: by 2002:a05:6214:5701:b0:914:5769:dcee with SMTP id 6a1803df08f44-91c48e36c9emr119685776d6.17.1793042283921; Mon, 26 Oct 2026 12:18:03 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-91c62063dacsm33430996d6.37.2026.10.26.12.18.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 12:18:03 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ray Jui , Scott Branden , Broadcom internal kernel review list , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Kishon Vijay Abraham I , Tejun Heo , Yendapally Reddy Dhananjaya Reddy , linux-ide@vger.kernel.org (open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-phy@lists.infradead.org (open list:GENERIC PHY FRAMEWORK) Subject: [PATCH v3 1/6] phy: broadcom: brcm-sata: Keep NSP ports in the shared PCB window Date: Mon, 26 Oct 2026 12:16:13 -0700 Message-ID: <20261026191618.3178830-2-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261026191618.3178830-1-florian.fainelli@broadcom.com> References: <20261026191618.3178830-1-florian.fainelli@broadcom.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Northstar Plus has one PCB register aperture for both SATA ports. Its per-port OOB settings use separate banks, while the PLL registers are shared. The 40nm MDIO refactor made all non-40nm platforms use a 0x1000 per-port stride. NSP previously passed the shared base directly to the helpers. For port 1, the new stride moves the bank selector from 0x1804033c to 0x1804133c in the AHCI register window, outside the PHY resource, and prevents the second PHY from being initialized correctly. Exclude NSP from the per-port aperture offset in both read and write helpers, preserving its existing bank selection. Fixes: 0ed41b33882c ("phy: brcm-sata: Correct MDIO operations for 40nm platforms") Signed-off-by: Florian Fainelli --- drivers/phy/broadcom/phy-brcm-sata.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/phy/broadcom/phy-brcm-sata.c b/drivers/phy/broadcom/phy-brcm-sata.c index fb69e21a0292..b5fb9dff1ae9 100644 --- a/drivers/phy/broadcom/phy-brcm-sata.c +++ b/drivers/phy/broadcom/phy-brcm-sata.c @@ -215,9 +215,10 @@ static void brcm_sata_phy_wr(struct brcm_sata_port *port, u32 bank, void __iomem *pcb_base = priv->phy_base; u32 tmp; + /* NSP has one shared PCB window; its per-port OOB banks are selected below. */ if (priv->version == BRCM_SATA_PHY_STB_40NM) bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); - else + else if (priv->version != BRCM_SATA_PHY_IPROC_NSP) pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE); writel(bank, pcb_base + SATA_PCB_BANK_OFFSET); @@ -233,7 +234,7 @@ static u32 brcm_sata_phy_rd(struct brcm_sata_port *port, u32 bank, u32 ofs) if (priv->version == BRCM_SATA_PHY_STB_40NM) bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); - else + else if (priv->version != BRCM_SATA_PHY_IPROC_NSP) pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE); writel(bank, pcb_base + SATA_PCB_BANK_OFFSET); -- 2.53.0