From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793055026; b=UYQwWCXw8CM7Ug+o7YW41KMgtMpOjCnnBxlUqAX54x9sfCfApfKM1a3yNttk2qxXmzA4 jRFOemU5Ez8L14wwWC/sN5vg7qDOH0LnNGqZsG3N85xImwWaV833BJ2eBFoACqw24Odkk 0BhJV+t6xKwIeC0hA6j++qe1KXhZxEHoVwvbTSvqYD2phboGFJEB+1SoR0PR7ZLvjP/RU lsOf+ZknI6O1+yAyDC69hSOR5A9epvdBfDMVI86uRfVJwWAtEF4aCYtEwZCPt1xtLV6iG zdijc1vA9cYcrHr4M9KH8PEWxYbCN0Ejg6HpXMabI+YhE5SAGTvsg6abaPn1qj8INCA== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793055026; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Transfer-Encoding; bh=ihw3Bqm4o/PW7VJdooatWq5HSHJoCtXrsM5cuvBGl8g=; b=JxKdHFiCA3YorUWBI/B5jo+UUPj52cDL6ZVvtCtTv87J7c7DcI1GjQpyDMUPa6DSX6VZ broUKVdnDjM6OKjvgbvn9xajFA7ADDa57EQb2Dp8FR7b7FTg4V7BQxQitZzOYIxj43o8R xiaKLlhJIJGqi0oWtjbisdBtStodYm12b8t8SQl7/d8wxbqrhiSmhhVTsXqVb9rIKDPF6 iSzbeA7HVBhv+HlNr9zNCBSyDCcOeDCrFTfpGvYkCVNagic/bLqMVEeYZ5DNYaCOUjSjH 8BkZiisQfmKoQPeeR2GfmmxATlyCEVRvyjXWdvYU/8Lpt573XfWSTNHl5ZluXNYF5FQ== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=e03i+DwE; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06BF4606A31E; Mon, 26 Oct 2026 22:50:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=e03i+DwE Received: by smtp.kernel.org (Postfix) with ESMTPSA id 947861F01825; Mon, 26 Oct 2026 22:50:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793055025; bh=ihw3Bqm4o/PW7VJdooatWq5HSHJoCtXrsM5cuvBGl8g=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=e03i+DwExwTvlUyblPM2EW6/pzoMPEsQ034Q2fLGxSenwUNzNKMACz0qpeSZKyhZZ 5kLbGHA7r9NtM970zRojnHnwhhUmbPf0OmjkNJrMtyZs46Z/XwwgzaKc4SM7N1Ec8z TQ5YGiv8vix5DCoyyTj/jeFwFXgIr9/bJIAEzUXihRn4v/32ct3eoJeaqt2t/87zT4 5e1XKB31SZAspXBEPlL4yp/2yCQUJkHFi1DpT/9YTf8d/XvVgMl3N71CHqzp6mOPBZ 6/sc+ni7/C3fXlQbQoNGdaNWn2aZVZ2wYgtKzm+vgnYXHuuusdqoJ5PW6ANPXOit2j iljWavcnOdytw== From: Vladimir Zapolskiy To: Bjorn Andersson , Konrad Dybcio , Abel Vesa , Bryan O'Donoghue , Vinod Koul , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , linux-media@vger.kernel.org, Neil Armstrong , Manivannan Sadhasivam , linux-phy@lists.infradead.org, Conor Dooley , devicetree@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH v2 5/7] arm64: dts: qcom: sm8450: Add CSI2 PHY device tree nodes Date: Tue, 27 Oct 2026 00:49:55 +0200 Message-ID: <20261026224957.1115370-6-vz@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20261026224957.1115370-1-vz@kernel.org> References: <20261026224957.1115370-1-vz@kernel.org> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add device tree nodes of six CAMSS CSIPHYs found on Qualcomm SM8450 SoC, and a shared CSIPHY OPP table for them. Reviewed-by: Bryan O'Donoghue Signed-off-by: Vladimir Zapolskiy --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 280 +++++++++++++++++++++++++++ 1 file changed, 280 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 05417cb5c4e5..f429dcaf1075 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -564,6 +564,22 @@ cluster_pd: power-domain-cpu-cluster0 { }; }; + csiphy_opp_table: opp-table-csiphy { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + }; + qup_opp_table_100mhz: opp-table-qup { compatible = "operating-points-v2"; @@ -3294,6 +3310,270 @@ cci1_i2c1: i2c-bus@1 { }; }; + csiphy0: phy@ace4000 { + compatible = "qcom,sm8450-csi2-phy", "qcom,x1e80100-csi2-phy"; + reg = <0 0x0ace4000 0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names = "core", + "timer", + "ahb"; + + interrupts = ; + + power-domains = <&camcc TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names = "top", + "mmcx", + "mx"; + + operating-points-v2 = <&csiphy_opp_table>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy0_in_ep: endpoint { + }; + }; + + port@1 { + reg = <1>; + + csiphy0_out_ep: endpoint { + }; + }; + }; + }; + + csiphy1: phy@ace6000 { + compatible = "qcom,sm8450-csi2-phy", "qcom,x1e80100-csi2-phy"; + reg = <0 0x0ace6000 0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names = "core", + "timer", + "ahb"; + + interrupts = ; + + power-domains = <&camcc TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names = "top", + "mmcx", + "mx"; + + operating-points-v2 = <&csiphy_opp_table>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy1_in_ep: endpoint { + }; + }; + + port@1 { + reg = <1>; + + csiphy1_out_ep: endpoint { + }; + }; + }; + }; + + csiphy2: phy@ace8000 { + compatible = "qcom,sm8450-csi2-phy", "qcom,x1e80100-csi2-phy"; + reg = <0 0x0ace8000 0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names = "core", + "timer", + "ahb"; + + interrupts = ; + + power-domains = <&camcc TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names = "top", + "mmcx", + "mx"; + + operating-points-v2 = <&csiphy_opp_table>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy2_in_ep: endpoint { + }; + }; + + port@1 { + reg = <1>; + + csiphy2_out_ep: endpoint { + }; + }; + }; + }; + + csiphy3: phy@acea000 { + compatible = "qcom,sm8450-csi2-phy", "qcom,x1e80100-csi2-phy"; + reg = <0 0x0acea000 0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names = "core", + "timer", + "ahb"; + + interrupts = ; + + power-domains = <&camcc TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names = "top", + "mmcx", + "mx"; + + operating-points-v2 = <&csiphy_opp_table>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy3_in_ep: endpoint { + }; + }; + + port@1 { + reg = <1>; + + csiphy3_out_ep: endpoint { + }; + }; + }; + }; + + csiphy4: phy@acec000 { + compatible = "qcom,sm8450-csi2-phy", "qcom,x1e80100-csi2-phy"; + reg = <0 0x0acec000 0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names = "core", + "timer", + "ahb"; + + interrupts = ; + + power-domains = <&camcc TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names = "top", + "mmcx", + "mx"; + + operating-points-v2 = <&csiphy_opp_table>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy4_in_ep: endpoint { + }; + }; + + port@1 { + reg = <1>; + + csiphy4_out_ep: endpoint { + }; + }; + }; + }; + + csiphy5: phy@acee000 { + compatible = "qcom,sm8450-csi2-phy", "qcom,x1e80100-csi2-phy"; + reg = <0 0x0acee000 0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names = "core", + "timer", + "ahb"; + + interrupts = ; + + power-domains = <&camcc TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names = "top", + "mmcx", + "mx"; + + operating-points-v2 = <&csiphy_opp_table>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy5_in_ep: endpoint { + }; + }; + + port@1 { + reg = <1>; + + csiphy5_out_ep: endpoint { + }; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,sm8450-camcc"; reg = <0 0x0ade0000 0 0x20000>; -- 2.51.0