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Thu, 29 Oct 2026 03:47:46 -0700 From: Jacky Huang To: CC: Subject: Re: [PATCH 2/2] ARM: dts: aspeed: Add NVIDIA MGX Vera C2 BMC Date: Thu, 29 Oct 2026 19:47:15 +0900 Message-ID: <20261029104721.817046-1-jackyhuang@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <0d221cbd11c8b582d43b21e4156dfb7c83b121b3.1793243187.git.jackyhuang@nvidia.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00018549:EE_|MN0PR12MB6245:EE_ X-MS-Office365-Filtering-Correlation-Id: 8cec103b-6803-4bd6-b1bc-08df35aa1b35 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|23010399003|376014|1800799024|22082099003|18002099003|6133799003|261026121527099003|56012099006|11063799006|4143699003|10067099003|261021121427099003|261022075727099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: CH1qBtbf8f2zKzwfU/hLIWPIBKgxcigVQFLeEmiauBTY+6DaZYA3URS9pTVo9CC5P+rTQyLicHN9Ng5d5K4iS+SDCjMWH8mdJf2iA98UPi3yrXC6Ychg5onFGt1NLV/Yfgvx9KCFbjJzlqxvMNZvv+uhrPplQ/IvGtFOb6p96LCWM37s63rEIQagLG3VnzOiSgetfnv38qtbDaNtPDawgIP6IHr8zA4B2gk1e+OXYkQTwKSO3PhyQeWLKt3fcGKW2K6cno7wwjvIm0Yb3y/cOqCBtkGaJKNUYneOnAZ8JXZQ5xYIdinyBHXxHAY5YCMcJC8VALAhEX3pZuZJY4/DDMsyXdVFz6gx0gUzrbwxK4NrpgGYO/4s0uYUHjFnwY249r1fRB/QbBkp5yGdsq1tjx4Vl+CtPJXmsp9u1X810i9UWpbO32acLcsWsMGDhr7S X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2026 10:48:02.5372 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8cec103b-6803-4bd6-b1bc-08df35aa1b35 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00018549.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6245 On Thu, Oct 29, 2026 at 05:13:56AM +0000, sashiko-bot@kernel.org wrote: > Similarly, further down in this file, the pca6408@20 expanders on > &i2c_mcio_c0_south0 and &i2c_mcio_c1_south0 define identical "GPU1_*" > gpio-line-names, and the pca6408@20 expanders on &i2c_mcio_c0c1_north3 and > &i2c_mcio_c0c1_north6 define identical "E1S_*" gpio-line-names. Should those > line names be disambiguated (for example with C1/C2 prefixes) so that > consumers can address both instances by name? These are alternative placements for different configurations. I'll drop the C1 ones in v2, so the DTS only describes the C2 board and the names become unique. [ ... ] > [Severity: High] > Should i2c-mux@70, i2c-mux@71, and i2c-mux@75 on &i2c4 include the > i2c-mux-idle-disconnect property (like the pca9546 muxes on &i2c6 and &i2c9)? The muxes on i2c4 intentionally don't use i2c-mux-idle-disconnect. Each of them carries MCTP-over-I2C channels, and MCTP endpoints send their responses back to the BMC as separate transfers through the selected channel. With idle-disconnect the channel is closed right after the request, so responses can get lost. So I'd like to keep them as is. Thanks, Jacky