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Sun, 01 Nov 2026 10:57:51 -0800 (PST) Received: from hp ([71.12.40.102]) by smtp.gmail.com with ESMTPSA id 00721157ae682-8b2b716d420sm40869397b3.33.2026.11.01.10.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Nov 2026 10:57:51 -0800 (PST) From: Tim Michals To: Jassi Brar , Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-sunxi@lists.linux.dev, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Tim Michals Subject: [PATCH v3 3/7] dt-bindings: remoteproc: Add Allwinner A523 RISC-V remote processor Date: Sun, 1 Nov 2026 12:57:31 -0600 Message-ID: <20261101185735.762559-4-tcmichals@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261101185735.762559-1-tcmichals@gmail.com> References: <20261101185735.762559-1-tcmichals@gmail.com> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Allwinner A523, A527 and T527 (sun55i) contain a T-Head XuanTie E906 RISC-V core. It runs from a dedicated 256 KiB SRAM and can use a second 256 KiB SRAM and DRAM; a bit in a PRCM remap register shares a further 512 KiB SRAM (SRAM A3_2) with its subsystem. Its reset vector is set in its configuration block. Describe the configuration block, both SRAMs and the remap register, the bus, core and SRAM clocks, the configuration, core, SRAM and debug resets, the RISC-V and SRAM power domains, one message box channel, the reserved memory regions (a pool for virtio, DRAM for firmware, a trace buffer) and an optional crash interrupt. Signed-off-by: Tim Michals --- Changes in v3: - File renamed to allwinner,sun55i-a523-rproc.yaml to match the compatible - reg and reg-names are a fixed list of four (cfg, sram-a3-0, sram-a3-1, remap), all required (Krzysztof); the SRAMs are named as in the T527 manual (SRAMA3_0, SRAMA3_1); the description says the remap bit shares SRAM A3_2, not SRAM space 1 - clocks and resets are fixed lists, no minItems (Krzysztof); add the debug reset. The msgbox and parent clocks and the msgbox reset are dropped: they belong to the message box node - Add the RISC-V and SRAM power domains - One message box channel; mbox-names dropped. mboxes is optional: a user can drive the message box from userspace (UIO) instead - The crash interrupt description says the A523 has no dedicated line for it; it is the only interrupt, so no interrupt-names - memory-region[0] is a shared-dma-pool; the example has the memory regions - "schema" dropped from the subject (Krzysztof) - Jernej Skrabec and Samuel Holland dropped from the maintainers; the MAINTAINERS entry moves to the driver patch --- .../allwinner,sun55i-a523-rproc.yaml | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/allwinner,sun55i-a523-rproc.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/allwinner,sun55i-a523-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/allwinner,sun55i-a523-rproc.yaml new file mode 100644 index 000000000000..b119acaa2df6 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/allwinner,sun55i-a523-rproc.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/allwinner,sun55i-a523-rproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A523 XuanTie E906 RISC-V Remote Processor + +maintainers: + - Tim Michals + +description: + The Allwinner A523, A527 and T527 (sun55i) SoCs contain a T-Head XuanTie + E906 RISC-V core next to the Cortex-A55 cluster. The core runs from a + dedicated 256 KiB SRAM, can also use a second 256 KiB SRAM and DRAM, + and a remap register shared with the HiFi4 DSP shares a further 512 KiB + SRAM (SRAM A3_2) with the core's subsystem. Its reset vector is set in a + register of its configuration block, and it exchanges notifications with + the Cortex-A55 host through the message box. + +properties: + compatible: + const: allwinner,sun55i-a523-rproc + + reg: + items: + - description: Configuration block, including the boot address register + - description: SRAM A3_0, the core's dedicated SRAM space 0 + - description: SRAM A3_1, the core's SRAM space 1 + - description: SRAM remap control register + + reg-names: + items: + - const: cfg + - const: sram-a3-0 + - const: sram-a3-1 + - const: remap + + clocks: + items: + - description: Configuration block bus clock + - description: RISC-V core clock + - description: MCU public SRAM bus clock + + clock-names: + items: + - const: bus + - const: core + - const: sram + + resets: + items: + - description: Configuration block reset + - description: RISC-V core reset + - description: MCU public SRAM reset + - description: RISC-V debug module reset + + reset-names: + items: + - const: cfg + - const: core + - const: sram + - const: debug + + mboxes: + description: + Message box channel to the RISC-V core. Each channel has a FIFO in + each direction, so it carries notifications both ways. + maxItems: 1 + + firmware-name: + maxItems: 1 + + memory-region: + minItems: 1 + items: + - description: Virtio vring and buffer pool, a shared-dma-pool + - description: Firmware code and data in DRAM + - description: Trace buffer + + memory-region-names: + minItems: 1 + items: + - const: vram + - const: dram + - const: trace + + interrupts: + maxItems: 1 + description: + Interrupt the RISC-V core raises on a fatal error. The A523 has no + dedicated line for this, so it is present only where the system + integration provides one. + + power-domains: + items: + - description: RISC-V core power domain + - description: SRAM power domain + + power-domain-names: + items: + - const: riscv + - const: sram + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + - power-domain-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + remoteproc@7130000 { + compatible = "allwinner,sun55i-a523-rproc"; + reg = <0x07130000 0x1000>, + <0x07280000 0x40000>, + <0x072c0000 0x40000>, + <0x07010364 0x4>; + reg-names = "cfg", "sram-a3-0", "sram-a3-1", "remap"; + clocks = <&mcu_ccu CLK_BUS_MCU_RISCV_CFG>, + <&mcu_ccu CLK_MCU_RISCV>, + <&mcu_ccu CLK_BUS_MCU_PUBSRAM>; + clock-names = "bus", "core", "sram"; + resets = <&mcu_ccu RST_BUS_MCU_RISCV_CFG>, + <&mcu_ccu RST_BUS_MCU_RISCV_CORE>, + <&mcu_ccu RST_BUS_MCU_PUBSRAM>, + <&mcu_ccu RST_BUS_MCU_RISCV_DEBUG>; + reset-names = "cfg", "core", "sram", "debug"; + power-domains = <&ppu PD_RISCV>, <&ppu PD_SRAM>; + power-domain-names = "riscv", "sram"; + mboxes = <&msgbox 9>; + memory-region = <&riscv_vram>, <&riscv_dram>; + memory-region-names = "vram", "dram"; + firmware-name = "riscv-firmware.elf"; + }; -- 2.53.0